MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 10

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

CAS Latency
between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to one, two, or three clocks.
and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a read command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in Figure 4. Table 5 indi-
cates the operating frequencies at which each CAS
latency setting can be used.
operation or incompatibility with future versions may
result.
Operating Mode
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
read and write bursts.
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
M2 applies to both READ and WRITE bursts; when
M9= 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (non-
burst) accesses.
Low Power Extended Mode Register Definition
functions beyond those controlled by the mode regis-
ter. These additional functions are special features of
the mobile device. They include Temperature Com-
pensated Self Refresh (TCSR) control, Partial Array Self
Refresh (PASR), and Output Drive Strength. Not pro-
gramming the extended mode register upon initializa-
tion will result in default settings for the Low Power
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
The CAS latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
The normal operating mode is selected by setting
Test modes and reserved states should not be used
When M9 = 0, the burst length programmed via M0-
The low power extended mode register controls the
10
features. The extended mode will default with the tem-
perature sensor enabled, full drive strength, and full
array refresh.
grammed via the Mode Register Set command (BA1 =
1, BA0 = 0) and re-tains the stored information until it
is programmed again or the device loses power.
Table 6:
COMMAND
COMMAND
COMMAND
SPEED
- 10
-75
- 8
The low power extended mode register is pro-
CLK
CLK
CLK
DQ
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
LATENCY = 1
ALLOWABLE OPERATING FREQUENCY (MHZ)
READ
READ
Figure 4: CAS Latency
READ
T0
T0
T0
CAS Latency = 1
CAS
t
t AC
LZ
CAS Latency
50
50
50
CAS Latency = 2
NOP
NOP
T1
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
D
LATENCY = 2
t OH
OUT
MOBILE SDRAM
CAS
©2003 Micron Technology, Inc. All rights reserved.
83.3
104
100
T2
NOP
T2
NOP
T2
t
t AC
256Mb: x32
LZ
D
t OH
OUT
PRELIMINARY
LATENCY = 3
T3
T3
NOP
D
t OH
OUT
CAS
DON’T CARE
UNDEFINED
133
125
100
T4