MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 5

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MT48H8M32LFB5-10:G

Manufacturer Part Number
MT48H8M32LFB5-10:G
Description
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet

Specifications of MT48H8M32LFB5-10:G

Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
17/8/7ns
Maximum Clock Rate
104MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
65mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Table 3:
FBGA Part Number System
nents have an abbreviated part marking that is differ-
ent from the part number. For a quick conversion of an
FBGA code, see the FBGA Part Marking Decoder on the
Micron web site, www.micron.com/decoder.
General Description
dynamic
268,435,456-bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the 67,108,864-bit banks is organized as
4,096 rows by 512 columns by 32 bits.
ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0, BA1 select the bank; A0–A11 select the row). The
address bits registered coincident with the READ or
WRITE command are used to select the starting col-
umn location for the burst access.
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
PART NUMBER
MT48LC8M32LFF5-8
MT48LC8M32LFF5-10
MT48LC8M32LFB5-8
MT48LC8M32LFB5-10
MT48V8M32LFF5-8
MT48V8M32LFF5-10
MT48V8M32LFB5-8
MT48V8M32LFB5-10
MT48H8M32LFF5-8
MT48H8M32LFF5-10
MT48H8M32LFB5-8
MT48H8M32LFB5-10
Due to space limitations, FBGA-packaged compo-
The Micron
Read and write accesses to the SDRAM are burst ori-
random-access
®
Cross Reference For VFBGA Device Marking
256Mb SDRAM is a high-speed CMOS,
V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
DD
memory
/V
DD
Q
ARCHITECTURE
containing
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
5
write burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless high-speed,
random-access operation.
2.5V, and 1.8V low-power memory systems. An auto
refresh mode is provided, along with a power-saving,
Deep Power-Down Mode. All inputs and outputs are
LVTTL-compatible.
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks in order to hide precharge
time and the capability to randomly change column
addresses on each clock cycle during a burst access.
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
The SDRAM provides for programmable read or
The 256Mb SDRAM uses an internal pipelined
The 256Mb SDRAM is designed to operate in 3.3V,
SDRAMs offer substantial advances in DRAM oper-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
VFBGA
ENGINEERING
SAMPLE
Z9CDD
Z9CCQ
Z9CDH
Z9CCG
Z9CCV
Z9CCX
Z9CCN
Z9CDB
Z9CCL
Z9CCS
Z9CCJ
MOBILE SDRAM
TBD
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
PRELIMINARY
PRODUCTION
MARKING
D9CCW
D9CCM
D9CCH
D9CCK
D9CDC
D9CCZ
D9CCP
D9CDF
D9CCR
D9CCT
D9CDL
D9CDJ

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