MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 24

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coin-
cident with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one
clock previous to the BURST TERMINATE command.
This is shown in Figure 22, where data n is the last
desired data element of a longer burst.
PRECHARGE
to deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (
after the precharge command is issued. Input A10
determines whether one or all banks are to be pre-
charged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are
treated as “Don’t Care.” Once a bank has been pre-
charged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank.
POWER-DOWN
dent with a NOP or COMMAND INHIBIT when no
accesses are in progress. If power-down occurs when
all banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates
the input and output buffers, excluding CKE, for maxi-
mum power savings while in standby. The device may
not remain in the power-down state longer than the
refresh period (64ms) since no refresh operations are
performed in this mode.
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting
DEEP POWER-DOWN
ings feature achieved by shutting off the power to the
entire memory array of the device. Data on the mem-
ory array will not be retained once Deep Power Down
mode is executed. Deep Power Down mode is entered
by having all banks idle then CS# and WE# held low
with RAS# and CAS# high at the rising edge of the
clock, while CKE is low. CKE must be held low during
Deep Power Down.
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
Fixed-length or full-page WRITE bursts can be trun-
The PRECHARGE command (see Figure 23) is used
Power-down occurs if CKE is registered low coinci-
The power-down state is exited by registering a NOP
Deep Power Down mode is a maximum power sav-
t
CKS). See Figure 24.
t
RP)
24
COMMAND
CKE
CLK
A0-A9, A11
Figure 22: Terminating a WRITE Burst
COMMAND
All banks idle
Enter power-down mode.
Figure 23: PRECHARGE Command
ADDRESS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BA0,1
NOTE:
RAS#
CAS#
WE#
CKE
CLK
A10
CS#
t CKS
CLK
DQ
Figure 24: Power-Down
NOP
HIGH
Input buffers gated off
DQMs are LOW.
BANK,
COL n
WRITE
D
VALID ADDRESS
T0
n
IN
(
(
(
(
)
(
)
)
)
)
(
(
(
)
(
)
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(
)
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MOBILE SDRAM
Exit power-down mode.
TERMINATE
©2003 Micron Technology, Inc. All rights reserved.
BURST
Bank Selected
T1
All Banks
ADDRESS
256Mb: x32
BANK
> t CKS
PRELIMINARY
NOP
COMMAND
(ADDRESS)
(DATA)
DON’T CARE
T2
NEXT
DON’T CARE
ACTIVE
t RCD
t RAS
t RC