MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 14

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 256Mb
SDRAM requires 4,096 AUTO REFRESH cycles every
64ms (
command every 15.625µs will meet the refresh
requirement and ensure that each row is refreshed.
Alternatively, 4,096 AUTO REFRESH commands can be
issued in a burst at the minimum cycle rate (
once every 64ms.
SELF REFRESH
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking. The
SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
Once the SELF REFRESH command is registered, all
the inputs to the SDRAM become “Don’t Care” with the
exception of CKE, which must remain LOW.
vides its own internal clocking, causing it to perform
its own auto refresh cycles. The SDRAM must remain
in self refresh mode for a minimum period equal to
t
inite period beyond that.
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
RAS and may remain in self refresh mode for an indef-
The addressing is generated by the internal refresh
The SELF REFRESH command can be used to retain
Once self refresh mode is engaged, the SDRAM pro-
t
REF). Providing a distributed AUTO REFRESH
t
RFC),
14
sequence of commands. First, CLK must be stable (sta-
ble clock is defined as a signal cycling within timing
constraints specified for the clock pin) prior to CKE
going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two
clocks) for
pletion of any internal refresh in progress.
commands must be issued every 15.625µs or less as
both SELF REFRESH and AUTO REFRESH utilize the
row refresh counter.
DEEP POWER DOWN
maximum power reduction by eliminating the power
of the whole memory array of the devices. Array data
will not be retained once the device enters Deep Power
Down Mode. The settings in the Mode and Extended
Mode register will be retained during Deep Power-
down.
CS# and WE# held low with RAS# and CAS# held high
at the rising edge of the clock, while CKE is low. This
mode is exited by asserting CKE high.
The procedure for exiting self refresh requires a
Upon exiting the self refresh mode, AUTO REFRESH
Deep Power Down is an operating mode to achieve
This mode is entered by having all banks idle then
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
XSR because time is required for the com-
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
PRELIMINARY