MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 13

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

EXTENDED MODE REGISTER commands can only be
issued when all banks are idle, and a subsequent exe-
cutable command cannot be issued until
EXTENDED MODE REGISTER will be retained even
when exiting Deep Power Down.
ACTIVE
a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0–A11 selects the row.
This row remains active (or open) for accesses until a
precharge command is issued to that bank. A pre-
charge command must be issued before opening a dif-
ferent row in the same bank.
READ
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0–A8 selects the starting column location. The
value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
read burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Read data
appears on the DQs subject to the logic level on the
DQM inputs two clocks earlier. If a given DQM signal
was registered HIGH, the corresponding DQs will be
High-Z two clocks later; if the DQM signal was regis-
tered LOW, the DQs will provide valid data.
WRITE
write access to an active row. The value on the BA0,
BA1 inputs selects the bank, and the address provided
on inputs A0–A8 selects the starting column location.
The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected,
the row being accessed will be precharged at the end of
the write burst; if auto precharge is not selected, the
row will remain open for subsequent accesses. Input
data appearing on the DQs is written to the memory
array subject to the DQM input logic level appearing
coincident with the data. If a given DQM signal is reg-
istered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the
corresponding data inputs will be ignored, and a write
will not be executed to that byte/column location.
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
The Values of the LOAD MODE REGISTER and
The ACTIVE command is used to open (or activate)
The READ command is used to initiate a burst read
The WRITE command is used to initiate a burst
t
MRD is met.
13
PRECHARGE
the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (
command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0,
BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
Auto Precharge
same individual-bank precharge function described
above, without requiring an explicit command. This is
accomplished by using A10 to enable auto precharge
in conjunction with a specific READ or WRITE com-
mand. A precharge of the bank/row that is addressed
with the READ or WRITE command is automatically
performed upon completion of the READ or WRITE
burst, except in the full-page burst mode, where auto
precharge does not apply. Auto precharge is non per-
sistent in that it is either enabled or disabled for each
individual Read or Write command.
ated at the earliest valid stage within a burst. The user
must not issue another command to the same bank
until the precharge time (
determined as if an explicit PRECHARGE command
was issued at the earliest possible time, as described
for each burst type in the Operation section of this
data sheet.
BURST TERMINATE
cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated,
as shown in the Operation section of this data sheet.
AUTO REFRESH
the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) refresh in conventional DRAMs. This command
is non persistent, so it must be issued each time a
refresh is required. All active banks must be PRE-
CHARGED prior to issuing an AUTO REFRESH com-
mand. The AUTO REFRESH command should not be
issued until the minimum
PRECHARGE command as shown in the operation sec-
tion.
The PRECHARGE command is used to deactivate
Auto precharge is a feature which performs the
Auto precharge ensures that the precharge is initi-
The BURST TERMINATE command is used to trun-
AUTO REFRESH is used during normal operation of
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MOBILE SDRAM
t
t
RP) is completed. This is
RP has been met after the
©2003 Micron Technology, Inc. All rights reserved.
t
RP) after the precharge
256Mb: x32
PRELIMINARY