MAX5858AECM+TD Maxim Integrated Products, MAX5858AECM+TD Datasheet - Page 18

• Manufacturer Part Number: MAX5858AECM+TD
• Description: IC DAC 10BIT DUAL 300MSPS 48TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5858AECM+TD

• Settling Time: 11ns
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 816mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX5858A features an on-chip PLL clock multiplier
that generates all internal, synchronized high-speed
clock signals required by the input data latches, inter-
polation filters, and DAC cores. The on-chip PLL
includes a phase-detector, VCO, prescalar, and
charge-pump circuits. The PLL can be enabled or dis-
abled through PLLEN. To enable PLL set PLLEN = 1.
With the PLL enabled (PLLEN = 1) and 4x/2x interpola-
tion enabled, an external low-frequency clock reference
source is applied to CLK pin. The clock reference
source serves as the input data clock. The on-chip PLL
multiplies the clock reference by a factor of two (2x) or
a factor of four (4x). The input data rate range and CLK
frequency are set by the selected interpolation mode.
In 2x interpolation mode, the data rate range is 75MHz
to 150MHz. In 4x interpolation mode the data rate
range is 37.5MHz to 75MHz.
Note: When the PLL is enabled, CLK becomes an
input, requiring CLKXP to be pulled low and CLKXN to
be pulled high. To obtain best phase noise perfor-
mance, disable the PLL function.
With the PLL disabled (PLLEN = 0) and 4x/2x interpola-
tion enabled, an external conversion clock is applied at
CLKXN/CLKXP. The conversion clock at CLKXN/CLKXP
has a frequency range of 0MHz to 300MHz (see Table
5). This clock is buffered and distributed by the
MAX5858A to drive the interpolation filters and DAC
cores. In this mode, CLK becomes a divide-by-N (DIV-
N) output at either a divide-by-two or divide-by-four
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
Figure 4. Setting IFS with the Internal 1.24V Reference and the Control Amplifier
18
*COMPENSATION CAPACITOR (C
______________________________________________________________________________________
AGND
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
COMP
PLL Clock Multiplier and
MAX4040
≈ 100nF).
I
REF
=
V
R
REF
SET
Clocking Modes
AGND
C
COMP
*
R
SET
REFO
REFR
I
REF
rate. The DIV-N factor is set by the selected interpola-
tion mode. The CLK output, at DIV-N rate, must be
used to synchronize data into the MAX5858A data
ports. In this mode, keep the capacitive load at the CLK
output low (10pF or less at f
With the interpolation disabled (1x mode) and the PLL
disabled (PLLEN = 0), the input clock at CLKXN/CLKXP
can be used to directly update the DAC cores. In this
mode, the maximum data rate is 165MHz.
The MAX5858A provides an integrated 50ppm/°C,
1.24V, low-noise bandgap reference that can be dis-
abled and overridden with an external reference volt-
age. REFO serves either as an external reference input
or an integrated reference output. If REN is connected
to AGND, the internal reference is selected and REFO
provides a 1.24V (50µA) output. Buffer REFO with an
external amplifier, when driving a heavy load.
The MAX5858A also employs a control amplifier
designed to simultaneously regulate the full-scale out-
put current (I
Calculate the output current as:
where I
V
is the reference resistor that determines the amplifier out-
put current of the MAX5858A (Figure 4). This current is
mirrored into the current-source array where I
distributed between matched current segments and
summed to valid output current readings for the DACs.
REFO
Internal Reference and Control Amplifier
/R
REF
SET
REFERENCE
BANDGAP
REN
) and I
1.24V
is the reference output current (I
FS
) for both outputs of the devices.
FS
MAX5858A
I
is the full-scale output current. R
FS
AGND
= 32
DAC
✕
I
REF
= 165MHz).
SOURCE ARRAY
CURRENT-
FS
is equally
REF
I
FS
SET
=