MAX5858AECM+TD Maxim Integrated Products, MAX5858AECM+TD Datasheet - Page 20

• Manufacturer Part Number: MAX5858AECM+TD
• Description: IC DAC 10BIT DUAL 300MSPS 48TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5858AECM+TD

• Settling Time: 11ns
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 816mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
Figure 6 depicts the write cycle of the MAX5858A in 4x
interpolation mode. With the interpolation feature
enabled, the device can operate with the PLL enabled
or disabled.
With the PLL disabled (PLLEN = 0), the clock signal is
applied to CLKXP/CLKXN and internally divided by 4 to
generate the DAC’s CLK signal. The CLK signal is a
divide-by-four output used to synchronize data into the
MAX5858A data ports. The CLKXP/CLKXN signal dri-
ves the interpolation filters and DAC cores at the
desired conversion rate.
If the PLL is enabled (PLLEN = 1), CLK becomes an
input and the clock signal is applied to CLK. In Figure
6, the CLK signal is multiplied by a factor of four by the
PLL and distributed to the interpolation filters and DAC
cores. In this mode, CLKXP must be pulled low and
CLKXN pulled high.
Figure 6. Timing Diagram for Noninterleave Data Mode (IDE = Low)
20
CONTROL WORD
______________________________________________________________________________________
DA0–DA9/
DB0–DB9
CLKXN
CLKXP
CLK
CW
1
1
2
1. CLKXP AND CLKXN MUST BE PRESENT WHEN PLL IS DISABLED, WITH PLLEN CONNECTED TO GND. THE DIAGRAM SHOWS 4x INTERPOLATION.
2. CLK IS AN OUTPUT WHEN PLL IS DISABLED WITH PLLEN CONNECTED TO GND, OTHERWISE, IT IS AN INPUT.
t
DCSR
t
CXD
DA
DB
N
N
t
CXD
The MAX5858A can operate with a single-ended clock
input used as both data clock and conversion clock. To
operate the device in this mode, disable the interpolation
filters and enable the PLL (PLLEN = 1). Apply a single-
ended clock input at CLK. The CLK signal acts as the
data synchronization clock and DAC core conversion
clock. Though the PLL is enabled, the lock pin (LOCK) is
not valid and the PLL is internally disconnected from
interpolating filters and DAC cores. In this mode, CLKXP
must be pulled low and CLKXN pulled high.
Figure 6 shows the timing for the control word write
pulse (CW). An 8-bit control word routed through chan-
nel A’s data port programs the gain matching, interpo-
lator configuration, and operational mode of the
MAX5858A. The control word is latched on the falling
edge of CW. The CW signal is asynchronous with con-
version clocks CLK and CLKXN/CLKXP; therefore, the
conversion clock (CLK or CLKXN/CLKXP) can run unin-
terrupted when a control word is written to the device.
CONTROL WORD
t
t
CWS
CWH
DA
DB
N+1
N+1
t
DCHR