MAX5858AECM+TD Maxim Integrated Products, MAX5858AECM+TD Datasheet - Page 21

• Manufacturer Part Number: MAX5858AECM+TD
• Description: IC DAC 10BIT DUAL 300MSPS 48TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5858AECM+TD

• Settling Time: 11ns
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 816mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX5858A can operate in interleave data mode by
setting IDE = 1. In interleave data mode, data for both
DAC channels is written through input port A. Channel
B data is written on the falling edge of the CLK signal
and then channel A data is written on the following ris-
ing edge of the CLK signal. Both DAC outputs (channel
A and B) are updated simultaneously on the next rising
edge of CLK. In interleave data mode, the maximum
input data rate per channel is one-half the rate of nonin-
terleave mode. Interleave data mode is an attractive
feature that lowers digital I/O pin count, reduces digital
ASIC cost and improves system reliability (Figure 7).
The MAX5858A exhibits excellent dynamic performance
to synthesize a wide variety of modulation schemes,
including high-order QAM modulation with OFDM.
Figure 8 shows a typical application circuit with output
transformers performing the required differential-to-sin-
gle-ended signal conversion. In this configuration, the
MAX5858A operates in differential mode, which
reduces even-order harmonics, and increases the avail-
able output power.
Figure 7. Timing Diagram for Interleave Data Mode (IDE = High)
DA0–DA9
Differential-to-Single-Ended Conversion
CLKXN
CLKXP
CLK
2
1
1
1. CLKXP AND CLKXN MUST BE PRESENT WHEN PLL IS DISABLED, WITH PLLEN CONNECTED TO GND. THE DIAGRAM SHOWS 4x INTERPOLATION.
2. CLK IS AN OUTPUT WHEN PLL IS DISABLED WITH PLLEN CONNECTED TO GND, OTHERWISE, IT IS AN INPUT.
Applications Information
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
______________________________________________________________________________________
t
DCSR
DA
t
N
CXD
DB
t
DCSF
N+1
Interpolation Filters and PLL
t
DCHF
t
CXD
Figure 8. Application with Output Transformer Performing
Differential to Single-Ended Conversion
DA
10
10
DA0–DA9
DB0–DB9
N+1
AGND
AV
DD
DGND
DV
MAX5858A
MAX5858A
DD
1/2
1/2
PGND
PV
DB
DD
N+2
OUTPA
OUTNA
OUTPB
OUTNB
50Ω
100Ω
50Ω
50Ω
100Ω
50Ω
DA
N+2
t
DCHR
SINGLE ENDED
SINGLE ENDED
V
V
OUTA
OUTB
,
,
21