MAX5858AECM+TD Maxim Integrated Products, MAX5858AECM+TD Datasheet - Page 4

• Manufacturer Part Number: MAX5858AECM+TD
• Description: IC DAC 10BIT DUAL 300MSPS 48TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5858AECM+TD

• Settling Time: 11ns
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 816mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
ELECTRICAL CHARACTERISTICS (continued)
(AV
V
guaranteed by production test. T
4
INTERPOLATION FILTER (4x interpolation)
Passband Width
Stopband Rejection
Group Delay
Impulse Response Duration
LOGIC INPUTS (IDE, CW, REN, DA9–DA0, DB9–DB0, PLLEN)
Digital Input-Voltage High
Digital Input-Voltage Low
Digital Input-Current High
Digital Input-Current Low
Digital Input Capacitance
DIGITAL OUTPUTS (CLK, LOCK)
Digital Output-Voltage High
Digital Output-Voltage Low
DIFFERENTIAL CLOCK INPUT (CLKXP, CLKXN)
Clock Input Internal Bias
Differential Clock Input Swing
Clock Input Impedance
TIMING CHARACTERISTICS
Input Data Rate
Clock Frequency at CLK Input
REFO
DD
_______________________________________________________________________________________
= 1.2V, I
= DV
PARAMETER
DD
FS
= PV
= 20mA, output amplitude = 0dB FS, differential output, T
DD
= 3V, AGND = DGND = PGND = 0, f
A
< +25°C guaranteed by design and characterization. Typical values are at T
SYMBOL
0.5f
f
f
V
DATA
f
OUT
C
V
V
V
CLK
I
I
OH
OL
H
IL
IH
IN
DAC
IL
/
-0.005dB
-0.01dB
-0.1dB
-3dB
0.302f
0.300f
0.297f
0.266f
V
V
I
I
Single-ended clock drive
No interpolation
2x interpolation
4x interpolation
No interpolation, PLL enabled
2x interpolation, PLL enabled
4x interpolation, PLL enabled
SOURCE
SINK
IH
IL
= 0.8V
= 2V
= 0.5mA, Figure 1
DAC
DAC
DAC
DAC
= 0.5mA, Figure 1
/ 2 to 1.698f
/ 2 to 1.700f
/ 2 to 1.703 f
/ 2 to 1.734f
DAC
CONDITIONS
= 165Msps, no interpolation, PLL disabled, external reference,
DAC
DAC
DAC
PLL disabled
PLL enabled
PLL disabled
PLL enabled
DAC
/ 2
/ 2
/ 2
A
/ 2
= T
MIN
to T
MAX
, unless otherwise noted. T
DV
0.9 ×
37.5
37.5
MIN
0.5
75
75
-1
-1
2
DD
PV
0.200
0.201
0.210
0.239
TYP
74
63
53
14
22
27
DD
3
5
/ 2
A
= +25°C.)
DV
MAX
0.1 ×
165
150
150
165
150
0.8
+1
+1
75
75
75
DD
A
> +25°C
UNITS
cycles
cycles
MHz/
clock
clock
Msps
MHz
Data
Data
MHz
V
dB
µA
µA
pF
kΩ
P-P
V
V
V
V
V