ADSP-21371KSWZ-2B Analog Devices Inc, ADSP-21371KSWZ-2B Datasheet
ADSP-21371KSWZ-2B
Specifications of ADSP-21371KSWZ-2B
Available stocks
Related parts for ADSP-21371KSWZ-2B
ADSP-21371KSWZ-2B Summary of contents
Page 1
... DEDICATED AUDIO COMPONENTS ADSP-21371—S/PDIF-compatible digital audio receiver/transmitter ADSP-21371—8 dual data line serial ports that operate Mbps on each data line — each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair ...
Page 2
... Added operating conditions and electrical characteristics for the 1.0 V, 200 MHz parts. For this revision the following sections have been removed. For information see the ADSP-2137x SHARC Processor Hardware Reference: “Address Data Pins as Flags”, “Address/Data Modes”, Core Instruction Rate to CLKIN Ratio Modes.” ...
Page 3
... TWI Package on Page 1, the pro- The diagram up the ADSP-2137x processors. The core clock domain contains the following features: • Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • ...
Page 4
... ADSP-21371/ADSP-21375 SHARC FAMILY CORE ARCHITECTURE The ADSP-21371/ADSP-21375 processors are code compatible at the assembly level with the ADSP-2136x, ADSP-2126x, ADSP-21160x, and ADSP-21161N, and with the first generation ADSP-2106x SHARC processors. The ADSP-21371/ ADSP-21375 processors share architectural features with the ADSP-2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC ...
Page 5
... On-Chip Memory The ADSP-21371 processor contains 1 megabit of internal RAM and four megabits of internal mask-programmable ROM (see Table 3 on Page megabits of internal RAM and two megabits of internal mask- programmable ROM (see configured for different combinations of code and data storage ...
Page 6
... The external port on the ADSP-21371/ADSP-21375 SHARC processors provide a high performance, glueless interface to a wide variety of industry-standard memory devices. The 32-bit wide bus (ADSP-21371) may be used to interface to synchro- nous and/or asynchronous memory devices through the use of its separate internal memory controllers: the first is an SDRAM ...
Page 7
... Table 4. ADSP-21375 Internal Memory Space IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Long Word (64 bits) Instruction Word (48 bits) BLOCK 0 ROM BLOCK 0 ROM 0x0004 0000–0x0004 3FFF 0x0008 0000–0x0008 5554 Reserved Reserved 0x0004 4000–0x0004 BFFF 0x0008 5555–0x0008 FFFF ...
Page 8
... ADSP-21371/ADSP-21375 SDRAM Controller The SDRAM controller provides an interface four sepa- rate banks of industry-standard SDRAM devices or DIMMs. Fully compliant with the SDRAM standard, each bank has its own memory select line (MS0–MS3), and can be configured to contain between 16M bytes and 256M bytes of memory. ...
Page 9
... SPORTs are enabled, or eight duplex TDM streams of 128 channels per frame. For the ADSP-21375, serial ports are enabled via eight program- mable pins and simultaneous receive or transmit pins that support transmit or 16 receive channels of audio data when all four SPORTs are enabled, or four duplex TDM streams of 128 channels per frame ...
Page 10
... DMA operations to occur while the core is simultaneously exe- cuting its program instructions. DMA transfers can occur between the ADSP-2137x processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the UART (see Table 7 ...
Page 11
... The processors provide delay line DMA functionality. This allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. Scatter/Gather DMA The ADSP-2137x processor provides scatter/gather DMA func- tionality. This allows processor DMA reads/writes to/from non- contiguous memory blocks. SYSTEM DESIGN The following sections provide an introduction to system design options and power supply issues ...
Page 12
... EZ-KIT Lite board enables high speed, non- intrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the processor’s architecture and functionality. For detailed information on the core architecture and instruction set, refer to the ADSP-2137x SHARC Processor Hardware Reference. Rev Page September 2009 ® evaluation plat- ...
Page 13
... External Data. The data pins can be multiplexed to support the external memory pulled high interface data (I/O), the PDAP (I) (PDAP for ADSP-21371), FLAGS (I/O) and PWM (O). After reset, all DATA pins are in EMIF mode and FLAG(0–3) pins are in FLAGS mode (default). ...
Page 14
... PMCTL register at any time after the core comes out of reset. Boot Configuration Select. These pins select the boot mode for the processor. The BOOT_CFG pins must be valid before reset is asserted. See the ADSP-2137x SHARC Processor Hardware Reference for information about boot modes. ...
Page 15
... CLKIN may not be halted, changed, or operated below the specified frequency. Reset Out/Running Reset In. The default setting is reset out. This pin also has a second function as RUNRSTIN, which is enabled by setting bit 0 of the RUNRSTCTL register. For more information, see the ADSP-2137x SHARC Processor Hardware Reference. Rev Page September 2009 ADSP-21371/ADSP-21375 ...
Page 16
... Input Capacitance IN 1 Specifications subject to change without notice. 2 Applies to output and bidirectional pins: ADDR23–0, DATA31–0 (DATA15–0 on ADSP-21375), RD, WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, and SDCLK. 3 See Output Drive Currents on Page 45 for typical drive current capabilities. ...
Page 17
... Silicon Revision yyww Date Code MAXIMUM POWER DISSIPATION See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2137x SHARC Processors” (EE-318) for detailed thermal and power information regarding maximum power dis- sipation. For information on package thermal specifications, see Thermal Characteristics on Page 46. ...
Page 18
... CLKIN 2 when the input divider is enabled INPUT Note the definitions of the clock periods that are a function of CLKIN and the appropriate ratio control shown in of the timing specifications for the ADSP-2137x peripherals are defined in relation to t for each peripheral’s timing information. VCO Table 12 ...
Page 19
... DDINT DDEXT Table 15. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097 t RSTVDD t IVDDEVDD t CLKVDD t CLKRST t PLLRST Figure 5. Power-Up Sequencing Rev Page September 2009 ADSP-21371/ADSP-21375 Min Max 0 –50 +200 0 200 4096 × × ...
Page 20
... Note that the clock rate is achieved using a 16.67 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. ADSP-2137x R1 XTAL CLKIN 1M * ...
Page 21
... Parameter Timing Requirements t Running RESET Pulse Width Low WRUNRST t Running RESET Setup Before CLKIN High SRUNRST CLKIN RUNRSTIN Min 4 × WRST Figure 8. Reset Min 4 × WRUNRST SRUNRST Figure 9. Running Reset Rev Page September 2009 ADSP-21371/ADSP-21375 Max Unit SRST Max Unit ns ns ...
Page 22
... ADSP-21371/ADSP-21375 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP pin). Table 17. Core Timer Parameter Switching Characteristic t TMREXP Pulse Width WCTIM FLAG3 (TMREXP) Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, ...
Page 23
... DPI_P14–1 (TIMER1–0) Min 2 × t – 2 PCLK t PWMO Figure 12. Timer PWM_OUT Timing Min 2 × t PCLK t PWI Figure 13. Timer Width Capture Timing Rev Page September 2009 ADSP-21371/ADSP-21375 Max Unit 31 2 × (2 – 1) × PCLK Max Unit 31 2 × (2 – 1) × PCLK ...
Page 24
... ADSP-21371/ADSP-21375 Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 21. DAI/DPI Pin to Pin Routing Parameter Timing Requirement t Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid DPIO DAI_Pm Min 1.5 DAI_Pn DPI_Pn DPI_Pm t DPIO Figure 14 ...
Page 25
... PCG Output Clock Delay After PCG Trigger DTRIGCLK t PCG Frame Sync Delay After PCG Trigger DTRIGFS 1 t Output Clock Period PCGOW D = FSxDIV FSxPHASE. For more information, see the ADSP-2137x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter. 1 Normal mode of operation. DAI_Pn DPI_Pn PCG_TRIGx_I DAI_Pm DPI_Pm ...
Page 26
... ADSP-21371/ADSP-21375 Flags The timing specifications provided below apply to the FLAG3–0 and DPI_P14–1 pins, and the DATA31–0 pins. See Page 13 for more information on flag use. Table 23. Flags Parameter Timing Requirement t DPI_P14–1, DATA31–0, FLAG3–0 FIPW Switching Characteristic t DPI_P14– ...
Page 27
... DATA (IN) DATA (OUT) CMND ADDR (OUT) Min 0.58 2.2 7 1.3 1.6 t SDCLK t SSDAT t HSDAT t DCAD t ENSDAT t DCAD t HCAD Figure 17. SDRAM Interface Timing for 133 MHz SDCLK Rev Page September 2009 ADSP-21371/ADSP-21375 1.2 V, 266 MHz Max Unit 5 5 SDCLKH t SDCLKL t DSDAT t HCAD ...
Page 28
... ADSP-21371/ADSP-21375 Memory Read—Bus Master Use these specifications for asynchronous interfacing to memo- ries. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. Table 25. Memory Read—Bus Master Parameter Timing Requirements t Address, Selects Delay to Data Valid ...
Page 29
... ACK (low). For asynchronous assertion of ACK (high) user must meet t t DAWH DDWH t DSAK t DAAK Figure 19. Memory Write—Bus Master Rev Page September 2009 ADSP-21371/ADSP-21375 1.2 V, 266 MHz Min Max t – 10 SDCLK W – 7.1 t – 3 SDCLK t – 2.7 SDCLK W – ...
Page 30
... ADSP-21371/ADSP-21375 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (SCLK) width. Table 27. Serial Ports—External Clock ...
Page 31
... DDTLFSE MCE = 1, MFD = Data Enable for MCE = 1, MFD = 0 DDTENFS 1 The t and t parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0. DDTLFSE DDTENFS Rev Page September 2009 ADSP-21371/ADSP-21375 1.2 V, 266 MHz Min Max Unit –1 ns 1.2 V, 266 MHz Min ...
Page 32
... ADSP-21371/ADSP-21375 DRIVE DAI_P20–1 (SCLK) DAI_P20–1 (FRAME SYNC) DAI_P20–1 (DATA CHANNEL A/B) DRIVE DAI_P20–1 (SCLK) DAI_P20–1 (FRAME SYNC) DAI_P20–1 (DATA CHANNEL A/B) NOTES 1. SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20–1 PINS USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20– ...
Page 33
... HFSI HOFSE DAI_P20–1 (FRAME SYNC) t HDTE DAI_P20–1 (DATA CHANNEL A/B) DRIVE EDGE SCLK t DDTTE Figure 21. Serial Ports Rev Page September 2009 ADSP-21371/ADSP-21375 DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE t SCLKW t DFSE t t SFSE HFSE t t SDRE HDRE DATA TRANSMIT—EXTERNAL CLOCK ...
Page 34
... ADSP-21371/ADSP-21375 Input Data Port (IDP) The timing requirements for the IDP are given in signals are routed to the DAI_P20–1 pins using the SRU. There- fore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 31. Input Data Port (IDP) ...
Page 35
... DATA DAI_P20–1 (PDAP_STROBE) Note that the 20-bits of external PDAP data can be provided through the external port DATA31–12 pins. On the ADSP-21375 processors, PDAP can not be multiplexed on the external port (since only DATA15–0). Use the SRU DAI instead. SAMPLE EDGE t ...
Page 36
... ADSP-21371/ADSP-21375 Pulse-Width Modulation Generators (PWM) For the ADSP-21371, the following timing specifications apply when the DATA31–16 pins are configured as PWM. Table 33. Pulse-Width Modulation (PWM) Timing Parameter Switching Characteristics t PWM Output Pulse Width PWMW t PWM Output Period PWMP PWM OUTPUTS Pulse-width modulation generator information does not apply to the ADSP-21375 ...
Page 37
... S/PDIF Transmitter For the ADSP-21371, serial data input to the S/PDIF transmitter 2 can be formatted as left-justified right-justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 25 shows the right-justified mode. LRCLK is high for the left channel and low for the right channel ...
Page 38
... ADSP-21371/ADSP-21375 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 34. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 34. S/PDIF Transmitter Input Data Timing ...
Page 39
... S/PDIF Receiver For the ADSP-21371, the following section describes timing as it relates to the S/PDIF receiver. Table 36. S/PDIF Receiver Internal Digital PLL Mode Timing Parameter Switching Characteristics t LRCLK Delay After Serial Clock DFSI t LRCLK Hold After Serial Clock HOFSI t Transmit Data Delay After Serial Clock ...
Page 40
... ADSP-21371/ADSP-21375 SPI Interface—Master The processor contains two SPI ports. Both primary and sec- ondary are available through DPI only. The timing provided in Table 37 and Table 38 applies to both. Table 37. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements t Data Input Valid To SPICLK Edge (Data Input Setup Time) ...
Page 41
... SPICLS t SPICLS t SPICHS t DDSPIDS MSB MSB VALID t DDSPIDS MSB t SSPIDS MSB VALID Figure 31. SPI Slave Timing Rev Page September 2009 ADSP-21371/ADSP-21375 1.2 V, 266 MHz Min Max 4 × t – 2 PCLK 2 × t – 2 PCLK 2 × t – 2 PCLK 2 × t PCLK 2 × t PCLK 2 × t PCLK ...
Page 42
... ADSP-21371/ADSP-21375 Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing Figure 32 describes UART port receive and transmit operations. The maximum baud rate is PCLK/16 where PCLK = 1/t shown in Figure 32 there is some latency between the Table 39. UART Port Parameter Timing Requirement 1 t Incoming Data Pulse Width ...
Page 43
... SUDAT LOW SUSTA HDSTA HIGH Sr t HDDAT Figure 33. Fast and Standard Mode Timing on the TWI Bus Rev Page September 2009 ADSP-21371/ADSP-21375 1 Fast Mode Max Min Max 100 0 400 0.6 1.3 0.6 0.6 0 100 0.6 1.3 n BUF ...
Page 44
... ADSP-21371/ADSP-21375 JTAG Test Access Port and Emulation Table 41. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP 1 t System Inputs Setup Before TCK High ...
Page 45
... Capacitance and Typical Output Rise Time (20 Min) vs. Load Capacitance. 3.3V, 25°C 3.47V, - 45°C 3.3V, 25°C 2.5 3.0 3.5 44. These include V LOAD 1.5V Rev Page September 2009 ADSP-21371/ADSP-21375 Figure 36). Figure 40 shows graphically Figure 38, Figure 39, and Figure 40 may not be linear 12 10 RISE ...
Page 46
... ADSP-21371/ADSP-21375 0.0488X - 1.5923 100 LOAD CAPACITANCE (pF) Figure 40. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The processor is rated for performance over the temperature range specified in Operating Conditions on Page Table 42 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to-board measure- ment complies with JESD51-8 ...
Page 47
... LQFP_EP PINOUT Table 43. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) Pin No. Signal Pin No DDINT 2 DATA28 54 3 DATA27 55 4 GND DDEXT 6 DATA26 58 7 DATA25 59 8 DATA24 60 9 DATA23 61 10 GND DDINT 12 DATA22 64 13 DATA21 65 14 DATA20 DDEXT 16 GND 68 17 DATA19 ...
Page 48
... ADSP-21371/ADSP-21375 Table 43. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) (Continued) Pin No. Signal Pin No. 45 DATA5 97 46 DATA2 98 47 DATA3 99 48 DATA0 100 49 DATA1 101 50 V 102 DDEXT 51 GND 103 52 V 104 DDINT Signal Pin No. Signal ADDR19 149 DAI_P5 (SD1A) ADDR20 ...
Page 49
... Table 44. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) Pin No. Signal Pin No DDINT GND DDEXT GND DDINT DDINT 23 GND DDINT 25 GND DATA15 79 28 DATA14 80 29 DATA13 81 30 DATA12 DDEXT 32 GND DDINT 34 GND 86 35 DATA11 87 36 DATA10 88 37 DATA9 89 38 DATA8 90 39 ...
Page 50
... ADSP-21371/ADSP-21375 Table 44. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) (Continued) Pin No. Signal Pin No. 45 DATA5 97 46 DATA2 98 47 DATA3 99 48 DATA0 100 49 DATA1 101 50 V 102 DDEXT 51 GND 103 52 V 104 DDINT Signal Pin No. Signal ADDR19 149 DAI_P5 (SD1A) ADDR20 ...
Page 51
... PIN 1 TOP VIEW (PINS DOWN) 52 104 53 VIEW A COMPLIANT TO JEDEC STANDARDS MS-026-BJB-HD (SW-208-1) Dimensions shown in millimeters Rev Page September 2009 ADSP-21371/ADSP-21375 25.50 REF 8.712 REF 157 156 * EXPOSED PAD BOTTOM VIEW (PINS UP) 105 105 104 0.27 0.50 0.22 BSC 0 ...
Page 52
... AD21375WYSWZ1xx –40ºC to 105ºC 1 Referenced temperature is ambient temperature. ORDERING GUIDE Temperature Model Range 2 ADSP-21371KSWZ-2A 0ºC to +70ºC 2 ADSP-21371KSWZ-2B 0ºC to +70º ADSP-21371BSWZ-2B -40ºC to +85ºC 2 ADSP-21375KSWZ-2B 0ºC to +70º ADSP-21375BSWZ-2B -40ºC to +85ºC 1 Referenced temperature is ambient temperature. ...