ADSP-21371KSWZ-2B Analog Devices Inc, ADSP-21371KSWZ-2B Datasheet - Page 20

IC DSP 32BIT 266MHZ 208-LQFP

ADSP-21371KSWZ-2B

Manufacturer Part Number
ADSP-21371KSWZ-2B
Description
IC DSP 32BIT 266MHZ 208-LQFP
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr

Specifications of ADSP-21371KSWZ-2B

Package / Case
208-LQFP
Interface
DAI, DPI
Operating Temperature
0°C ~ 70°C
Clock Rate
266MHz
Non-volatile Memory
ROM (512 kB)
On-chip Ram
128kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Mounting Type
Surface Mount
Svhc
No SVHC (18-Jun-2010)
Base Number
21371
Core Frequency Typ
266MHz
Dsp Type
Floating Point
Mmac
532
No. Of Pins
208
Interface Type
SPI, UART
Rohs Compliant
Yes
Operating Temperature Range
0°C To +70°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21371KSWZ-2B
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-21371KSWZ-2B
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADSP-21371/ADSP-21375
Clock Input
Table 14. Clock Input
1
2
Clock Signals
The processor can use an external clock or a crystal. See the
CLKIN pin description in
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL.
component connections used for a crystal operating in funda-
mental mode. Note that the clock rate is achieved using a 16.67
MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN
achieves a clock speed of 266 MHz). To achieve the full core
clock rate, programs need to configure the multiplier bits in the
PMCTL register.
Parameter
Timing Requirements
t
t
t
t
t
f
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in the PMCTL register.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CK
CKL
CKH
CKRF
CCLK
VCO
CLKIN
2
Figure 7. 266 MHz Operation (Fundamental Mode Crystal)
C1
22pF
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
CLKIN
16.67 MHz
t
CKH
Figure 6. Clock Input
R1
1M *
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
VCO Frequency
Y1
Table
ADSP-2137x
9. Programs can configure the
XTAL
t
CK
R2
47 *
C2
22pF
t
CKL
Figure 7
Rev. C | Page 20 of 52 | September 2009
shows the
CCLK
.
Min
22.5
11.25
11.25
3.75
200
1
1
1
266 MHz
Max
100
45
45
6
10
800
Unit
ns
ns
ns
ns
ns
MHz

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