ADSP-21371KSWZ-2B Analog Devices Inc, ADSP-21371KSWZ-2B Datasheet - Page 19

• Manufacturer Part Number: ADSP-21371KSWZ-2B
• Description: IC DSP 32BIT 266MHZ 208-LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21371KSWZ-2B

• Package / Case: 208-LQFP
• Interface: DAI, DPI
• Operating Temperature: 0°C ~ 70°C
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 21371
• Core Frequency Typ: 266MHz
• Dsp Type: Floating Point
• Mmac: 532
• No. Of Pins: 208
• Interface Type: SPI, UART
• Rohs Compliant: Yes
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power-Up Sequencing
The timing requirements for processor startup are given in
Table
Note that during power-up, a leakage current of approximately
200 μA may be observed on the RESET pin. This leakage current
results from the weak internal pull-up resistor on this pin being
enabled during power-up.
Table 13. Power Up Sequencing Timing Requirements (Processor Startup)
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristic
t
Valid V
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time. Assume
Based on CLKIN cycles.
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
The 4096 cycle count depends on t
RSTVDD
IVDDEVDD
CLKVDD
CLKRST
PLLRST
CORERST
depending on the design of the power supply subsystem.
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
propagate default states at all I/O pins.
cycles maximum.
13.
1
DDINT
/V
DDEXT
CLK_CFG1–0
RESETOUT
assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
RESET
V
V
CLKIN
DDINT
DDEXT
RESET Low Before V
V
CLKIN Valid After V
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
Core Reset Deasserted After RESET Deasserted
DDINT
SRST
on Before V
specification in
t
RSTVDD
DDEXT
DDINT
DDINT
Table
/V
/V
DDEXT
DDEXT
Rev. C | Page 19 of 52 | September 2009
15. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
t
IVDDEVDD
Valid
On
Figure 5. Power-Up Sequencing
t
CLKVDD
t
PLLRST
t
CLKRST
Min
0
–50
0
10
20
4096 × t
2
3
t
CK
CORERST
ADSP-21371/ADSP-21375
+ 2 × t
CCLK
4, 5
Max
+200
200
Unit
ns
ms
ms
μs
μs