ADSP-21371KSWZ-2B Analog Devices Inc, ADSP-21371KSWZ-2B Datasheet - Page 9

• Manufacturer Part Number: ADSP-21371KSWZ-2B
• Description: IC DSP 32BIT 266MHZ 208-LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21371KSWZ-2B

• Package / Case: 208-LQFP
• Interface: DAI, DPI
• Operating Temperature: 0°C ~ 70°C
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 21371
• Core Frequency Typ: 266MHz
• Dsp Type: Floating Point
• Mmac: 532
• No. Of Pins: 208
• Interface Type: SPI, UART
• Rohs Compliant: Yes
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon-
figurable signal paths.
In the ADSP-21371, the DAI includes eight serial ports, four
precision clock generators (PCG), and an input data port (IDP).
For the ADSP-21375, the DAI includes four serial ports, four
precision clock generators (PCG) and an input data port (IDP).
The IDP provides an additional input path to the core of the
processor, configurable as either eight channels of I
data, or a single 20-bit wide synchronous parallel data acquisi-
tion port. Each data channel has its own DMA channel that is
independent from the processor’s serial ports.
Serial Ports
The processors feature eight synchronous serial ports on the
ADSP-21371 and four on the ADSP-21375. The SPORTs pro-
vide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.
For the ADSP-21371, serial ports are enabled via 16 program-
mable pins and simultaneous receive or transmit pins that
support up to 32 transmit or 32 receive channels of audio data
when all eight SPORTs are enabled, or eight duplex TDM
streams of 128 channels per frame.
For the ADSP-21375, serial ports are enabled via eight program-
mable pins and simultaneous receive or transmit pins that
support up to 16 transmit or 16 receive channels of audio data
when all four SPORTs are enabled, or four duplex TDM streams
of 128 channels per frame.
The serial ports operate at a maximum data rate of 50 Mbps.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig-
nals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
Serial ports operate in five modes:
Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var-
ious attributes of this mode.
Each of the serial ports supports the left-justified sample pair
and I
monly used by audio codecs, ADCs, and DACs such as the
• Standard DSP serial mode
• Multichannel (TDM) mode with support for packed I
• I
• Packed I
• Left-justified sample pair mode
mode
2
2
S protocols (I
S mode
2
S mode
2
S is an industry-standard interface com-
Rev. C | Page 9 of 52 | September 2009
2
S serial
2
S
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I
devices) per serial port, with a maximum of up to 32 I
nels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I
word lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional -law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be inter-
nally or externally generated.
The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/recep-
tion of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The ADSP-21371 S/PDIF receiver/transmitter has no separate
DMA channels. It receives audio data in serial format and con-
verts it into a biphase encoded signal. The serial data input to
the receiver/transmitter can be formatted as left justified, I
right justified with word widths of 16, 18, 20, or
24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources such as the
SPORTs, external pins, the precision clock generators (PCGs),
and are controlled by the SRU control registers.
The ADSP-21375 does not have an S/PDIF-compatible digital
receiver/transmitter.
Input Data Port (IDP)
The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
audio channels in I
mode. One frame sync cycle indicates one 64-bit left/right pair,
but data is sent to the FIFO as 32-bit words (that is, one-half of a
frame at a time). The processor supports 24- and 32-bit I
and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justi-
fied formats.
Precision Clock Generator (PCG)
The precision clock generators (PCG) consist of four units, each
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A B, C, and D, are
identical in functionality and operate independently of each
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.
2
S, left-justified sample pair, or right-justified
ADSP-21371/ADSP-21375
2
S channels (using two stereo
2
S modes, data-
2
S chan-
2
S, 24-
2
S or