EP3C25F324C8N Altera, EP3C25F324C8N Datasheet - Page 121
![IC CYCLONE III FPGA 25K 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C25F324C8N
Manufacturer Part Number
EP3C25F324C8N
Description
IC CYCLONE III FPGA 25K 324-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C25F324C8N.pdf
(274 pages)
Specifications of EP3C25F324C8N
Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
215
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
24624
# I/os (max)
215
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
24624
Ram Bits
608256
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2078
EP3C25F324C8NES
EP3C25F324C8NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C25F324C8N
Manufacturer:
ALTERA
Quantity:
2 350
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EP3C25F324C8N
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ALTERA
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Part Number:
EP3C25F324C8NES
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 6: I/O Features in the Cyclone III Device Family
Pad Placement and DC Guidelines
Pad Placement and DC Guidelines
Pad Placement
DC Guidelines
Chapter Revision History
Table 6–7. Chapter Revision History (Part 1 of 3)
© December 2009
December 2009
July 2009
June 2009
October 2008
Date
f
Altera Corporation
Altera recommends that you create a Quartus II design, enter your device I/O
assignments, and compile your design to validate your pin placement. The Quartus II
software checks your pin connections with respect to the I/O assignment and
placement rules to ensure proper device operation. These rules are dependent on
device density, package, I/O assignments, voltage assignments, and other factors that
are not fully described in this chapter.
For more information about how the Quartus II software checks I/O restrictions, refer
to the
For the Quartus II software to automatically check for illegally placed pads according
to the DC guidelines, set the DC current sink or source value to Electromigration
Current assignment on each of the output pins that are connected to the external
resistive load.
The programmable current strength setting has an impact on the amount of DC
current that an output pin can source or sink. Determine if the current strength setting
is sufficient for the external resistive load condition on the output pin.
Table 6–7
Version
3.2
3.1
3.0
2.1
I/O Management
lists the revision history for this chapter.
Minor changes to the text.
Made minor correction to the part number.
Updated to include Cyclone III LS information
■
■
■
■
■
■
■
■
■
Updated chapter part number.
Updated “Introduction” on page 6–1, “PCI-Clamp Diode” on page 6–6, “On-
Chip Series Termination Without Calibration” on page 6–10, “I/O Standards”
on page 6–11, “I/O Banks” on page 6–16, “High-Speed Differential
Interfaces” on page 6–20, and “External Memory Interfacing” on page 6–20.
Updated Table 6–6 on page 6–18.
Added (Note 6) to Table 6–5.
Updated the “I/O Banks” section.
Updated the “Differential Pad Placement Guidelines” section.
Updated the “V
Removed any mention of “RSDS and PPDS are registered trademarks of
National Semiconductor” from chapter.
Updated chapter to new template.
chapter in volume 2 of the Quartus II Handbook.
REF
Pad Placement Guidelines” section.
Changes Made
Cyclone III Device Handbook, Volume 1
6–21