EP3C25F324C8N Altera, EP3C25F324C8N Datasheet - Page 24
![IC CYCLONE III FPGA 25K 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C25F324C8N
Manufacturer Part Number
EP3C25F324C8N
Description
IC CYCLONE III FPGA 25K 324-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C25F324C8N.pdf
(274 pages)
Specifications of EP3C25F324C8N
Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
215
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
24624
# I/os (max)
215
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
24624
Ram Bits
608256
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2078
EP3C25F324C8NES
EP3C25F324C8NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C25F324C8N
Manufacturer:
ALTERA
Quantity:
2 350
Company:
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Manufacturer:
ALTERA
Quantity:
160
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Part Number:
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612
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Manufacturer:
ALTERA/阿尔特拉
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Part Number:
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Manufacturer:
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Quantity:
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1–10
JTAG Boundary Scan Testing
Quartus II Software Support
Configuration
Cyclone III Device Handbook, Volume 1
f
f
f
Cyclone III device family supports the JTAG IEEE Std. 1149.1 specification. The
boundary-scan test (BST) architecture offers the capability to test pin connections
without using physical test probes and captures functional data while a device is
operating normally. Boundary-scan cells in the Cyclone III device family can force
signals onto pins or capture data from pins or from logic array signals. Forced test
data is serially shifted into the boundary-scan cells. Captured data is serially shifted
out and externally compared to expected results. In addition to BST, you can use the
IEEE Std. 1149.1 controller for the Cyclone III LS device in-circuit reconfiguration
(ICR).
For more information about JTAG boundary scan testing, refer to the
(JTAG) Boundary Scan Testing for Cyclone III Devices
The Quartus II software is the leading design software for performance and
productivity. It is the only complete design solution for CPLDs, FPGAs, and ASICs in
the industry. The Quartus II software includes an integrated development
environment to accelerate system-level design and seamless integration with leading
third-party software tools and flows.
The Cyclone III LS devices provide both physical and functional separation between
security critical design partitions. Cyclone III LS devices offer isolation between
design partitions. This ensures that device errors do not propagate from one partition
to another, whether unintentional or intentional. The Quartus II software design
separation flow facilitates the creation of separation regions in Cyclone III LS devices
by tightly controlling the routing in and between the LogicLock regions. For ease of
use, the separation flow integrates in the existing incremental compilation flow.
For more information about the Quartus II software features, refer to the
Handbook.
Cyclone III device family uses SRAM cells to store configuration data. Configuration
data is downloaded to Cyclone III device family each time the device powers up.
Low-cost configuration options include the Altera EPCS family serial flash devices as
well as commodity parallel flash configuration options. These options provide the
flexibility for general-purpose applications and the ability to meet specific
configuration and wake-up time requirements of the applications. Cyclone III device
family supports the AS, PS, FPP, and JTAG configuration schemes. The AP
configuration scheme is only supported in Cyclone III devices.
For more information about configuration, refer to the
and Remote System Upgrades in Cyclone III Devices
chapter.
chapter.
Chapter 1: Cyclone III Device Family Overview
Configuration, Design Security,
© December 2009 Altera Corporation
Cyclone III Device Family Architecture
IEEE 1149.1
Quartus II