EP3C25F324C8N Altera, EP3C25F324C8N Datasheet - Page 82
![IC CYCLONE III FPGA 25K 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C25F324C8N
Manufacturer Part Number
EP3C25F324C8N
Description
IC CYCLONE III FPGA 25K 324-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C25F324C8N.pdf
(274 pages)
Specifications of EP3C25F324C8N
Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
215
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
24624
# I/os (max)
215
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
24624
Ram Bits
608256
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2078
EP3C25F324C8NES
EP3C25F324C8NES
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Manufacturer
Quantity
Price
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Quantity:
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5–18
Clock Switchover
Cyclone III Device Handbook, Volume 1
f
If you use the SignalTap
locked signal goes low only when areset is deasserted. If the areset signal is not
enabled, the extra logic is not implemented in the ALTPLL megafunction.
For more information about the PLL control signals, refer to the
User
The clock switchover feature allows the PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application,
such as a system that turns on the redundant clock if the previous clock stops
running. Your design can automatically perform clock switchover when the clock is
no longer toggling, or based on the user control signal, clkswitch.
Automatic Clock Switchover
Cyclone III device family PLLs support a fully configurable clock switchover
capability.
When the current reference clock is not present, the clock-sense block automatically
switches to the backup clock for PLL reference. The clock switchover circuit also
sends out three status signals—clkbad[0], clkbad[1], and activeclock—from
the PLL to implement a custom switchover circuit. You can select a clock source at the
backup clock by connecting it to the inclk1 port of the PLL in your design.
Figure 5–14
Figure 5–14. Automatic Clock Switchover Circuit
Guide.
inclk1
inclk0
shows the block diagram of the switchover circuit built into the PLL.
muxout
®
II tool to probe the locked signal before the D flip-flop, the
clksw
n Counter
Sense
Clock
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
refclk
Switchover
Machine
State
© December 2009 Altera Corporation
PFD
ALTPLL Megafunction
clkswitch
(provides manual
switchover support)
fbclk
clkbad0
clkbad1
Activeclock
Hardware Features