EP3C25F324C8N Altera, EP3C25F324C8N Datasheet - Page 170
![IC CYCLONE III FPGA 25K 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C25F324C8N
Manufacturer Part Number
EP3C25F324C8N
Description
IC CYCLONE III FPGA 25K 324-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C25F324C8N.pdf
(274 pages)
Specifications of EP3C25F324C8N
Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
215
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
24624
# I/os (max)
215
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
24624
Ram Bits
608256
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2078
EP3C25F324C8NES
EP3C25F324C8NES
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9–10
Configuration Scheme
Cyclone III Device Handbook, Volume 1
1
the Enable user supplied start-up clock option (CLKUSR) option, the CLKUSR pin is
the initialization clock source. Supplying a clock on the CLKUSR pin does not affect
the configuration process. After the configuration data is accepted and CONF_DONE
goes high, the Cyclone III device family requires a certain amount of clock cycles to
initialize and to enter user mode.
Table 9–5
family.
Table 9–5. Initialization Clock Cycles Required in Cyclone III Device Family
Table 9–6
Table 9–6. Maximum CLKUSR Frequency for Cyclone III Device Family
If you use the optional CLKUSR pin and the nCONFIG pin is pulled low to restart
configuration during device initialization, ensure that the CLKUSR pin continues to
toggle when nSTATUS is low (a maximum of 230 μs).
User Mode
An optional INIT_DONE pin is available that signals the end of initialization and the
start of user mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software from the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it is high due to an external
10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. After the option bit to enable INIT_DONE is programmed into the
device (during the first frame of configuration data), the INIT_DONE pin goes low.
When initialization is complete, the INIT_DONE pin is released and pulled high. This
low-to-high transition signals that the device has entered user mode. In user mode,
the user I/O pins function as assigned in your design and no longer have weak
pull-up resistors.
A configuration scheme with different configuration voltage standards is selected by
driving the MSEL pins either high or low, as listed in
The MSEL pins are powered by V
pull-down resistors that are always active.
Cyclone III LS
Cyclone III LS
Cyclone III
Cyclone III
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Device
Device
lists the required clock cycles for proper initialization in Cyclone III device
lists the maximum CLKUSR frequency (f
CCINT
. The MSEL[3..0] pins have 9-kΩ internal
Initialization Clock Cycles
f
MAX
MAX
3,185
3,192
133
100
(MHz)
Table
) for Cyclone III device family.
© December 2009 Altera Corporation
9–7.
Configuration Features