EP3C25F324C8N Altera, EP3C25F324C8N Datasheet - Page 69
![IC CYCLONE III FPGA 25K 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C25F324C8N
Manufacturer Part Number
EP3C25F324C8N
Description
IC CYCLONE III FPGA 25K 324-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C25F324C8N.pdf
(274 pages)
Specifications of EP3C25F324C8N
Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
215
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
24624
# I/os (max)
215
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
24624
Ram Bits
608256
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2078
EP3C25F324C8NES
EP3C25F324C8NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
ALTERA
Quantity:
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Part Number:
EP3C25F324C8NES
Manufacturer:
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Quantity:
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
Figure 5–1. Clock Control Block
Notes to
(1) The clkswitch signal can either be set through the configuration file or dynamically set when using the manual PLL switchover feature. The
(2) The clkselect[1..0] signals are fed by internal logic and is used to dynamically select the clock source for the GCLK when the device is in
(3) The static clock select signals are set in the configuration file. Therefore, dynamic control when the device is in user mode is not feasible.
(4) You can use internal logic to enable or disable the GCLK in user mode.
© December 2009
output of the multiplexer is the input clock (f
user mode.
Figure
CLK[n + 3]
CLK[n + 2]
CLK[n + 1]
CLK[n]
f
5–1:
Altera Corporation
Figure 5–1
Each PLL generates five clock outputs through the c[4..0] counters. Two of these
clocks can drive the GCLK through a clock control block, as shown in
For more information about how to use the clock control block in the Quartus
software, refer to the
inclk1
inclk0
Static Clock Select (3)
CLKSWITCH (1)
shows the clock control block.
IN
) for the PLL.
f
IN
DPCLK or CDPCLK
ALTCLKCTRL Megafunction User
PLL
Internal Logic
C0
C1
C2
C3
C4
CLKSELECT[1..0] (2)
Clock Control Block
Static Clock
Select (3)
Guide.
Cyclone III Device Handbook, Volume 1
Internal Logic (4)
Enable/
Disable
Figure
Global
Clock
5–1.
®
II
5–5