EP3C25F324C8N Altera, EP3C25F324C8N Datasheet - Page 88
![IC CYCLONE III FPGA 25K 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C25F324C8N
Manufacturer Part Number
EP3C25F324C8N
Description
IC CYCLONE III FPGA 25K 324-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C25F324C8N.pdf
(274 pages)
Specifications of EP3C25F324C8N
Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
215
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
24624
# I/os (max)
215
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
24624
Ram Bits
608256
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2078
EP3C25F324C8NES
EP3C25F324C8NES
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Manufacturer
Quantity
Price
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Quantity:
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5–24
PLL Cascading
Figure 5–19. PLL Cascading Using GCLK
PLL Reconfiguration
Cyclone III Device Handbook, Volume 1
Output from PLL
Control Blocks
Five Clock
from two Clock
pins at adjacent
edge of device
Remote clock
CLK[0..3]
Two PLLs are cascaded to each other through the clock network. If your design
cascades PLLs, the source (upstream) PLL must have a low-bandwidth setting, while
the destination (downstream) PLL must have a high-bandwidth setting.
Figure 5–19
PLLs use several divide counters and different VCO phase taps to perform frequency
synthesis and phase shifts. In Cyclone III device family PLLs, you can reconfigure
both counter settings and phase shift the PLL output clock in real time. You can also
change the charge pump and loop filter components, which dynamically affects PLL
bandwidth. You can use these PLL components to update the output clock frequency,
PLL bandwidth, and phase shift in real time, without reconfiguring the entire FPGA.
2
PLL
PLL
2
3
1
5
1
Output from PLL
GCLK[0..4]
shows using GCLK while cascading PLLs.
20
GCLK[0:19]
Input to PLL
5
2
2
GCLK[15..19]
Control Blocks
GCLK[0:19]
Five Clock
CLK[8..11]
CLK[12..15]
1
20
4
GCLK[10..14]
20
1
Control Blocks
GCLK[0:19]
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Five Clock
GCLK[0:19]
2
2
Output from PLL
GCLK[5..9]
5
20
1
© December 2009 Altera Corporation
PLL
PLL
2
5
4
2
2
CLK[4..7]
4
Output from PLL
Five Clock
Control Blocks
PLL Cascading