EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 111
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Clock Networks and PLLs in Arria II GX Devices
PLLs in Arria II GX Devices
© July 2010
Altera Corporation
Figure 5–13. Source-Synchronous Mode for LVDS Compensation
No-Compensation Mode
In no-compensation mode, the PLL does not compensate for the clock networks. This
mode provides better jitter performance because the clock feedback into the phase
frequency detector (PFD) passes through less circuitry. Both the PLL internal- and
external-clock outputs are phase-shifted with respect to the PLL clock input.
Figure 5–14
no-compensation mode.
Figure 5–14. Phase Relationship Between PLL Clocks in No Compensation Mode
Note to
(1) The PLL clock outputs can lag the PLL input clocks depending on routine delays.
Figure
External PLL Clock Outputs (1)
5–14:
shows an example waveform of the PLL clocks’ phase relationship in
Register Clock Port (1)
Clock at register
reference clock
Data at register
PLL Clock at the
PLL Reference
at input pin
Clock at the
Data pin
Input Pin
PLL
Phase Aligned
Arria II GX Device Handbook, Volume 1
5–19
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