EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 190
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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8–6
Figure 8–2. LVDS SERDES and DPA Block Diagram
Notes to
(1) This diagram shows a shared PLL between the transmitter and receiver. If the transmitter and receiver are not sharing the same PLL, two PLLs
(2) In SDR and DDR modes, the data width is 1 and 2, respectively.
(3) The tx_in and rx_out ports have a maximum data width of 10.
Arria II GX Device Handbook, Volume 1
on the right side of the device are required.
rx_outclock
rx_divfwdclk
Figure
tx_coreclock
FPGA
Fabric
rx_out
tx_in 10
8–2:
10
3
(LOAD_EN, diffioclk)
IOE Supports SDR, DDR, or
2
(LVDS_LOAD_EN, diffioclk,
DIN DOUT
Non-Registered Datapath
Deserializer
DOUT
Serializer
tx_coreclock)
DIN
IOE
Center/Corner PLL
2
2
Clock Multiplexer
3
DOUT
(LVDS_LOAD_EN,
Bit Slip
LVDS_diffioclk,
IOE
rx_outclock
diffioclk
DIN
(Note
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
1), (2),
rx_inclock/tx_inclock
(3)
DOUT
Synchronizer
IOE Supports SDR, DDR, or
Non-Registered Datapath
DIN
8 Serial LVDS
Clock Phases
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
Retimed
DPA Clock
Data
DPA Circuitry
LVDS SERDES and DPA Block Diagram
LVDS Transmitter
DIN
LVDS Receiver
© July 2010 Altera Corporation
+
-
LVDS Clock Domain
DPA Clock Domain
+
-
rx_in
tx_out
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