EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 95
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Clock Networks and PLLs in Arria II GX Devices
Clock Networks in Arria II GX Devices
Figure 5–2. RCLK Networks in Arria II GX Devices
Notes to
(1) PLL_5 and PLL_6 are only available in EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
(2) RCLK[0..11] is not driven by any clock pins because there are no dedicated clock pins on the left side of the Arria II GX devices.
Periphery Clock Networks
© July 2010
Figure
Top Left PLL
Bottom Left PLL
Altera Corporation
5–2:
1
PLL_1
PLL_4
PCLK networks are a collection of individual clock networks driven from the
periphery of the Arria II GX device. Clock outputs from the DPA block,
PLD-transceiver interface clocks, horizontal I/O pins, and internal logic can drive the
PCLK networks.
The number of PCLKs for each Arria II GX device are as follows:
■
■
■
These PCLKs have higher skew when compared with the GCLK and RCLK networks
and can be used instead of general purpose routing to drive signals into the
Arria II GX device.
The legal clock sources for PCLK networks are clock outputs from the DPA block,
PLD-transceiver interface clocks, horizontal I/O pins, and internal logic.
RCLK[6..11]
EP2AGX45 and EP2AGX65 devices contain 50 PCLKs
EP2AGX95 and EP2AGX125 devices contain 59 PCLKs
EP2AGX190 and EP2AGX260 devices contain 84 PCLKs
RCLK[0..5]
(2)
(2)
RCLK[42..47]
RCLK[12..17]
CLK[12..15]
Q1
Q4
CLK[4..7]
RCLK[36..41]
Q2
Q3
RCLK[18..23]
RCLK[30..35]
RCLK[24..29]
PLL_3
PLL_2
PLL_5
PLL_6
Arria II GX Device Handbook, Volume 1
Bottom Right PLL
Top Right PLL
(1)
(1)
Center PLLs
CLK[8..11]
5–3
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