EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 254
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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9–34
Jam STAPL
Device Configuration Pins
Table 9–10. Arria II GX Configuration Pin Summary (Part 1 of 2)
Arria II GX Device Handbook, Volume 1
TDI
TMS
TCK
Description
f
Figure 9–18
microprocessor.
Figure 9–18. JTAG Configuration of a Single Device Using a Microprocessor
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Arria II GX devices in the chain.
(2) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you use only the
(3) You must connect nCE to GND or drive it low for successful JTAG configuration.
(4) To drive the JTAG pins, the microprocessor must use the same I/O standard as V
Jam standard test and programming language (STAPL), JEDEC standard JESD-71, is a
standard file format for in-system programmability (ISP) purposes. Jam STAPL
supports programming or configuration of programmable devices and testing of
electronic systems, using the IEEE 1149.1 JTAG interface. It is a freely licensed open
standard.
The Jam Player provides an interface for manipulating the IEEE Std. 1149.1 JTAG TAP
state machine.
For more information about JTAG and Jam STAPL in embedded environments, refer
to
download the jam player, visit the
Table 9–10
configuration-related pins on the Arria II GX devices.
configuration pins and their power supply.
AN 425: Using Command-Line Jam STAPL Solution for Device
The V
I/O on the device.
JTAG configuration, connect nCONFIG to the V
MSEL[3..0] to GND. Pull DCLK either high or low, whichever is convenient on your board.
Figure
CCIO
power supply of the bank in which the pin resides must be high enough to meet the V
through
shows a JTAG configuration of an Arria II GX device using a
9–18:
Input/Output
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Input
Input
Input
Microprocessor
Table 9–13
ADDR
Memory
DATA
describe the connections and functionality of all the
Dedicated
Yes
Yes
Yes
Altera
CCIO
power supply of the bank in which the pin resides and
website.
TDI (4)
TCK (4)
TMS (4)
TDO (4)
Arria II GX Device
CONF_DONE
Powered By
MSEL[3..0]
nSTATUS
nCONFIG
(3) nCE
V
V
V
DCLK
nCEO
CCIO
CCIO
CCIO
Table 9–10
V CCIO (1)
(2)
(2)
(2)
N.C.
GND
10 kΩ
CCIO
Programming. To
© July 2010 Altera Corporation
V CCIO (1)
.
lists the Arria II GX
Configuration Mode
10 kΩ
Device Configuration Pins
IH
JTAG
JTAG
JTAG
specification of the
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