EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 157
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 6: I/O Features in Arria II GX Devices
Arria II GX Design Considerations
I/O Placement Guidelines
Pin Placement Guideline
© July 2010 Altera Corporation
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards
An I/O bank can support both non-voltage-referenced and voltage-referenced pins by
applying each of the rule sets individually. For example, an I/O bank can support
SSTL-18 inputs and 1.8-V inputs and outputs with a 1.8-V V
Similarly, an I/O bank can support 1.5-V standards, 1.8-V inputs (but not outputs),
and HSTL and HSTL-15 I/O standards with a 1.5-V V
This section provides I/O placement guidelines for the programmable I/O standards
supported by Arria II GX devices and includes essential information for designing
systems with an Arria II GX device’s selectable I/O capabilities.
3.3-V, 3.0-V, and 2.5-V LVTTL/LVCMOS Tolerance Guidelines
Altera recommends the following techniques when you use 3.3-, 3.0-, and 2.5-V I/O
standards to limit overshoot and undershoot at I/O pins:
■
■
■
■
Altera recommends creating a Quartus II design, enter your device I/O assignments,
and compile your design to validate your pin placement. The Quartus II software
checks your pin connections with respect to I/O assignment and placement rules to
ensure proper device operation. These rules are dependent on device density,
package, I/O assignments, voltage assignments, and other factors that are not
described in this chapter.
Low drive strength or series termination—The impedance of the I/O driver must
be equal to or greater than the board trace impedance to minimize overshoot and
undershoot at the un-terminated receiver end. If high driver strength (lower driver
impedance) is required, Altera recommends series termination at the driver end
(on-chip or off-chip).
Output slew rate—Arria II GX devices have two levels of slew rate control for
single-ended output buffers. Slow slew rate can significantly reduce the overshoot
and undershoot in the system at the cost of slightly slower performance.
Input clamping diodes—Arria II GX I/Os have on-chip clamping diodes.
When you use clamping diodes, the floating well of the I/O is clamped to V
a result, the Arria II GX device might draw extra input leakage current from the
external input driver. This may violate the hot-socket DC- and AC-current
specification and increase power consumption. With the clamping diode enabled,
the Arria II GX device supports a maximum DC current of 8 mA.
CCIO
and 0.75-V V
Arria II GX Device Handbook, Volume 1
CCIO
and a 0.9-V V
REF
.
REF
CCIO
.
. As
6–23
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