MPC857DSLVR50B Freescale Semiconductor, MPC857DSLVR50B Datasheet - Page 36

• Manufacturer Part Number: MPC857DSLVR50B
• Description: IC MPU POWERQUICC 50MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC857DSLVR50B

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC85xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bus Signal Timing
Table 8
Figure 24
Figure 25
36
provides interrupt timing for the MPC862/857T/857DSL.
1
defined as level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or
negated with reference to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry,
and has no direct relation with the total system interrupt latency that the MPC862/857T/857DSL is able to
support.
provides the interrupt detection timing for the external level-sensitive lines.
provides the interrupt detection timing for the external edge-sensitive lines.
Num
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being
CLKOUT
CLKOUT
I39
I40
I41
I42
I43
IRQx
IRQx
Figure 24. Interrupt Detection Timing for External Level Sensitive Lines
Figure 25. Interrupt Detection Timing for External Edge Sensitive Lines
IRQx valid to CLKOUT rising edge (set up time)
IRQx hold time after CLKOUT
IRQx pulse width low
IRQx pulse width high
IRQx edge-to-edge time
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
Characteristic
Table 8. Interrupt Timing
1
I39
I43
I41
I40
4xT
I43
CLOCKOUT
6.00
2.00
3.00
3.00
Min
All Frequencies
I42
Max
Freescale Semiconductor
Unit
ns
ns
ns
ns
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