MPC857DSLVR50B Freescale Semiconductor, MPC857DSLVR50B Datasheet - Page 52

• Manufacturer Part Number: MPC857DSLVR50B
• Description: IC MPU POWERQUICC 50MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC857DSLVR50B

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC85xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CPM Electrical Characteristics
11.6
Table 19
52
Num
TIN/TGATE
78A
80A
71a
70
71
72
73
74
75
76
77
78
79
80
81
82
83
(Output)
(Input)
provides the serial interface timings as shown in
TOUT
CLKO
Serial Interface AC Electrical Specifications
L1RCLK, L1TCLK frequency (DSC = 0)
L1RCLK, L1TCLK width low (DSC = 0)
L1RCLK, L1TCLK width high (DSC = 0)
L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time
L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC setup time)
time)
L1RXD valid to L1CLK edge (L1RXD setup time)
L1CLK edge to L1RXD invalid (L1RXD hold time)
L1CLK edge to L1ST(1–4) valid
L1SYNC valid to L1ST(1–4) valid
L1CLK edge to L1ST(1–4) invalid
L1CLK edge to L1TXD valid
L1TSYNC valid to L1TXD valid
L1CLK edge to L1TXD high impedance
L1RCLK, L1TCLK frequency (DSC =1)
L1RCLK, L1TCLK width low (DSC =1)
L1CLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold
L1RSYNC, L1TSYNC rise/fall time
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
Figure 51. CPM General-Purpose Timers Timing Diagram
61
Characteristic
61
4
4
Table 19. SI Timing
2
1, 2
3
60
65
63
Figure 52
64
though
P + 10
P + 10
P + 10
20.00
35.00
17.00
13.00
10.00
10.00
10.00
10.00
10.00
0.00
Min
—
—
—
—
All Frequencies
62
Figure
SYNCCLK/2.5
SYNCCLK/2
16.00 or
56.
15.00
15.00
45.00
45.00
45.00
55.00
55.00
42.00
Freescale Semiconductor
Max
—
—
—
—
—
—
—
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns