MPC857DSLVR50B Freescale Semiconductor, MPC857DSLVR50B Datasheet - Page 44

• Manufacturer Part Number: MPC857DSLVR50B
• Description: IC MPU POWERQUICC 50MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC857DSLVR50B

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC85xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

IEEE 1149.1 Electrical Specifications
Figure 35
10 IEEE 1149.1 Electrical Specifications
Table 13
44
Num
J82
J83
J84
J85
J86
J87
J88
J89
J90
J91
J92
J93
J94
J95
J96
provides the JTAG timings for the MPC862/857T/857DSL shown in
DSCK, DSDI
provides the reset timing for the debug port configuration.
TCK cycle time
TCK clock pulse width measured at 1.5 V
TCK rise and fall times
TMS, TDI data setup time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO data invalid
TCK low to TDO high impedance
TRST assert time
TRST setup time to TCK low
TCK falling edge to output valid
TCK falling edge to output valid out of high impedance
TCK falling edge to output high impedance
Boundary scan input valid to TCK rising edge
TCK rising edge to boundary scan input invalid
CLKOUT
SRESET
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
Figure 35. Reset Timing—Debug Port Configuration
Characteristic
R80
Table 13. JTAG Timing
R70
R81
R82
R80
100.00
100.00
40.00
25.00
40.00
50.00
50.00
0.00
5.00
0.00
Min
—
—
—
—
—
All Frequencies
Figure 36
R81
10.00
27.00
20.00
50.00
50.00
50.00
Freescale Semiconductor
Max
—
—
—
—
—
—
—
—
—
though
Figure
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
39.