MPC857DSLVR50B Freescale Semiconductor, MPC857DSLVR50B Datasheet - Page 48

IC MPU POWERQUICC 50MHZ 357-PBGA

MPC857DSLVR50B

Manufacturer Part Number
MPC857DSLVR50B
Description
IC MPU POWERQUICC 50MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC857DSLVR50B

Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Processor Series
MPC85xx
Core
MPC8xx
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Operating Supply Voltage
2.5 V, 3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465/3.6V
Operating Supply Voltage (min)
2/3.135V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC857DSLVR50B
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MPC857DSLVR50B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
CPM Electrical Characteristics
11.2
Table 15
Figure 45
11.3
Table 16
48
Num
Num
35
36
40
41
42
provides the timings for port C interrupts.
provides the IDMA controller timings as shown in
Port C Interrupt AC Electrical Specifications
IDMA Controller AC Electrical Specifications
shows the port C interrupt detection timing.
DATA-OUT
Port C interrupt pulse width low (edge-triggered mode)
Port C interrupt minimum time between active edges
DREQ setup time to clock high
DREQ hold time from clock high
SDACK assertion delay from clock high
(Input)
DATA-IN
Port C
CLKO
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
Figure 44. Parallel I/O Data-In/Data-Out Timing Diagram
Figure 45. Port C Interrupt Detection Timing
Characteristic
Characteristic
Table 16. IDMA Controller Timing
Table 15. Port C Interrupt Timing
35
29
31
Figure 46
though
30
36
Min
All Frequencies
Min
55
55
7
3
Figure
33.34 MHz
Freescale Semiconductor
49.
Max
Max
12
Unit
Unit
ns
ns
ns
ns
ns

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