A80386DX33 Intel, A80386DX33 Datasheet - Page 111

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

6 2 2 32-Bit Extensions of the
With the Intel386 DX the 8086 80186 80286 in-
struction set is extended in two orthogonal direc-
tions 32-bit forms of all 16-bit instructions are added
to support the 32-bit data types and 32-bit address-
ing modes are made available for all instructions ref-
erencing memory This orthogonal instruction set ex-
tension is accomplished having a Default (D) bit in
the code segment descriptor and by having 2 prefix-
es to the instruction set
Whether the instruction defaults to operations of 16
bits or 32 bits depends on the setting of the D bit in
the code segment descriptor which gives the de-
fault length (either 32 bits or 16 bits) for both oper-
ands and effective addresses when executing that
code segment In the Real Address Mode or Virtual
8086 Mode no code segment descriptors are used
but a D value of 0 is assumed internally by the In-
tel386 DX when operating in those modes (for 16-bit
default sizes compatible with the 8086 80186
80286)
Two prefixes the Operand Size Prefix and the Effec-
tive Address Size Prefix allow overriding individually
the Default selection of operand size and effective
address size These prefixes may precede any op-
code bytes and affect only the instruction they pre-
cede If necessary one or both of the prefixes may
be placed before the opcode bytes The presence of
the Operand Size Prefix and the Effective Address
Prefix will toggle the operand size or the effective
address size respectively to the value ‘‘opposite’’
from the Default setting For example if the default
operand size is for 32-bit data operations then pres-
ence of the Operand Size Prefix toggles the instruc-
tion to 16-bit data operation As another example if
the default effective address size is 16 bits pres-
ence of the Effective Address Size prefix toggles the
instruction to use 32-bit effective address computa-
tions
These 32-bit extensions are available in all Intel386
DX modes including the Real Address Mode or the
Virtual 8086 Mode In these modes the default is
always 16 bits so prefixes are needed to specify
32-bit operands or addresses For instructions with
more than one prefix the order of prefixes is unim-
portant
Unless specified otherwise instructions with 8-bit
and 16-bit operands do not affect the contents of
the high-order bits of the extended registers
6 2 3 Encoding of Instruction Fields
Within the instruction are several fields indicating
register selection addressing mode and so on The
exact encodings of these fields are defined immedi-
ately ahead
Instruction Set
6 2 3 1 ENCODING OF OPERAND LENGTH (w)
For any given instruction performing a data opera-
tion the instruction is executing as a 32-bit operation
or a 16-bit operation Within the constraints of the
operation size the w field encodes the operand size
as either one byte or the full operation size as
shown in the table below
6 2 3 2 ENCODING OF THE GENERAL
The general register is specified by the reg field
which may appear in the primary opcode bytes or as
the reg field of the ‘‘mod r m’’ byte or as the r m
field of the ‘‘mod r m’’ byte
reg Field
w Field
000
001
010
011
100
101
110
111
reg
000
001
010
011
100
101
110
111
0
1
Encoding of reg Field When w Field
Encoding of reg Field When w Field
FIELD
REGISTER (reg) FIELD
Register Specified by reg Field
During 16-Bit Data Operations
Intel386
is not Present in Instruction
Register Selected Register Selected
Data Operations
Data Operations
is Present in Instruction
(when w
Operand Size
During 16-Bit
During 16-Bit
16 Bits
8 Bits
AH
CH
DH
BH
AL
CL
DL
BL
DX
AX
CX
BX
SP
BP
DI
TM
SI
Function of w Field
e
DX MICROPROCESSOR
0)
Data Operations
Data Operations
(when w
Operand Size
During 32-Bit
During 32-Bit
32 Bits
8 Bits
EAX
ECX
EDX
EBX
ESP
EBP
EDI
ESI
DX
AX
CX
BX
SP
BP
DI
SI
e
1)
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