A80386DX33 Intel, A80386DX33 Datasheet - Page 40

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

Intel386
4 3 4 4 LDT DESCRIPTORS (S
LDT descriptors (S
tion about Local Descriptor Tables LDTs contain a
table of segment descriptors unique to a particular
task Since the instruction to load the LDTR is only
available at privilege level 0 the DPL field is ignored
LDT descriptors are only allowed in the Global De-
scriptor Table (GDT)
4 3 4 5 TSS DESCRIPTORS (S
A Task State Segment (TSS) descriptor contains in-
formation about the location size and privilege level
of a Task State Segment (TSS) A TSS in turn is a
special fixed format segment which contains all the
state information for a task and a linkage field to
permit nesting tasks The TYPE field is used to indi-
cate whether the task is currently BUSY (i e on a
chain of active tasks) or the TSS is available The
TYPE field also indicates if the segment contains a
80286 or an Intel386 DX TSS The Task Register
(TR) contains the selector which points to the cur-
rent Task State Segment
4 3 4 6 GATE DESCRIPTORS (S
Gates are used to control access to entry points
within the target code segment The various types of
40
31
Name
Type
P
DPL least privileged level at which a task may access the gate WORD COUNT 0 –31 the number of parameters to copy from caller’s stack
to the called procedure’s stack The parameters are 32-bit quantities for Intel386
DESTINATION
SELECTOR
DESTINATION
OFFSET
SELECTOR
OFFSET 31
TYPE
TYPE
TM
DX MICROPROCESSOR
e
e
1 3 9 B)
4 –7 C F)
Value
4
5
6
7
C
E
F
0
1
16-bit
selector
offset
16-bit 80286
32-bit Intel386
16
e
0 TYPE
24
Gate Descriptor Fields
TM
e
DX
e
e
2) contain informa-
e
0 TYPE
0
80286 call gate
Task gate (for 80286 or Intel386
80286 interrupt gate
80286 trap gate
Intel386
Intel386
Intel386
Descriptor contents are not valid
Descriptor contents are valid
Selector to the target code segment
or
Selector to the target task state segment for task gate
Entry point within the target code segment
Figure 4-8 Gate Descriptor Formats
0
TM
TM
TM
e
DX call gate
DX interrupt gate
DX trap gate
2)
Description
16
OFFSET 15
P
DPL
gate descriptors are call gates task gates inter-
rupt gates and trap gates Gates provide a level of
indirection between the source and destination of
the control transfer This indirection allows the proc-
essor to automatically perform protection checks It
also allows system designers to control entry points
to the operating system Call gates are used to
change privilege levels (see section 4 4 Protection)
task gates are used to perform a task switch and
interrupt and trap gates are used to specify interrupt
service routines
Figure 4-8 shows the format of the four types of gate
descriptors Call gates are primarily used to transfer
program control to a more privileged level The call
gate descriptor consists of three fields the access
byte a long pointer (selector and offset) which
points to the start of a routine and a word count
which specifies how many parameters are to be cop-
ied from the caller’s stack to the stack of the called
routine The word count field is only used by call
gates when there is a change in the privilege level
other types of gates ignore the word count field
Interrupt and trap gates use the destination selector
and destination offset fields of the gate descriptor as
a pointer to the start of the interrupt or trap handler
routines The difference between interrupt gates and
trap gates is that the interrupt gate disables inter-
rupts (resets the IF bit) while the trap gate does not
TM
DX task)
TM
0
DX gates and 16-bit quantities for 80286 gates
0
TYPE
8
0
0
5
0 COUNT
WORD
4
0
0
a
0
4