A80386DX33 Intel, A80386DX33 Datasheet - Page 33

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

All of the Intel386 DX instructions are available in
Real Mode (except those instructions listed in 4 6 4)
The default operand size in Real Mode is 16-bits
just like the 8086 In order to use the 32-bit registers
and addressing modes override prefixes must be
used In addition the segment size on the Intel386
DX in Real Mode is 64K bytes so 32-bit effective
addresses must have a value less the 0000FFFFH
The primary purpose of Real Mode is to set up the
processor for Protected Mode Operation
The LOCK prefix on the Intel386 DX even in Real
Mode is more restrictive than on the 80286 This is
due to the addition of paging on the Intel386 DX in
Protected Mode and Virtual 8086 Mode Paging
makes it impossible to guarantee that repeated
string instructions can be LOCKed The Intel386 DX
can’t require that all pages holding the string be
physically present in memory Hence a Page Fault
(exception 14) might have to be taken during the
repeated string instruction Therefore the LOCK pre-
fix can’t be supported during repeated string instruc-
tions
These are the only instruction forms where the
LOCK prefix is legal on the Intel386 DX
An exception 6 will be generated if a LOCK prefix is
placed before any instruction form or opcode not
listed above The LOCK prefix allows indivisible
BIT Test and
XCHG
XCHG
ADD OR ADC SBB
NOT NEG INC DEC
SET RESET COMPLEMENT
AND SUB XOR
Opcode
Figure 3-1 Real Address Mode Addressing
Mem Reg immed
Reg Mem
Mem Reg
Mem Reg immed
Mem
(Dest Source)
Operands
read modify write operations on memory operands
using the instructions above For example even the
ADD Reg Mem is not LOCKable because the Mem
operand is not the destination (and therefore no
memory read modify operation is being performed)
Since on the Intel386 DX repeated string instruc-
tions are not LOCKable it is not possible to LOCK
the bus for a long period of time Therefore the
LOCK prefix is not IOPL-sensitive on the Intel386
DX The LOCK prefix can be used at any privilege
level but only on the instruction forms listed above
3 2 MEMORY ADDRESSING
In Real Mode the maximum memory size is limited to
1 megabyte Thus only address lines A2 – A19 are
active (Exception the high address lines A20 – A31
are high during CS-relative memory cycles until an
intersegment jump or call is executed (see section
2 10))
Since paging is not allowed in Real Mode the linear
addresses are the same as physical addresses
Physical addresses are formed in Real Mode by
adding the contents of the appropriate segment reg-
ister which is shifted left by four bits to an effective
address This addition results in a physical address
from 00000000H to 0010FFEFH This is compatible
with 80286 Real Mode Since segment registers are
shifted left by 4 bits this implies that Real Mode seg-
ments always start on 16 byte boundaries
All segments in Real Mode are exactly 64K bytes
long and may be read written or executed The
Intel386 DX will generate an exception 13 if a data
operand or instruction fetch occurs past the end of a
segment (i e if an operand has an offset greater
than FFFFH for example a word with a low byte at
FFFFH and the high byte at 0000H )
Intel386
TM
DX MICROPROCESSOR
231630 –54
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