A80386DX33 Intel, A80386DX33 Datasheet - Page 64

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

Intel386
5 2 6 Bus Control Signals (ADS
5 2 6 1 INTRODUCTION
The following signals allow the processor to indicate
when a bus cycle has begun and allow other system
hardware to control address pipelining data bus
width and bus cycle termination
5 2 6 2 ADDRESS STATUS (ADS )
This three-state output indicates that a valid bus cy-
cle definition and address (W R
BE0 –BE3
Intel386 DX pins It is asserted during T1 and T2P
bus states (see 5 4 3 2 Non-pipelined Address and
5 4 3 4 Pipelined Address for additional information
on bus states)
5 2 6 3 TRANSFER ACKNOWLEDGE (READY )
This input indicates the current bus cycle is com-
plete and the active bytes indicated by BE0 –
BE3
READY
interrupt acknowledge cycle the Intel386 DX latches
the input data and terminates the cycle When
READY
the processor terminates the bus cycle
READY
cycles and sampled each bus state thereafter until
asserted READY
acknowledge every bus cycle including Halt Indica-
tion and Shutdown Indication bus cycles When be-
ing sampled READY must always meet setup and
64
M IO
High
High
High
High
Low
Low
Low
Low
and BS16
READY
TM
is sampled asserted during a read cycle or
is sampled asserted during a write cycle
is ignored on the first bus state of all bus
DX MICROPROCESSOR
and A2 – A31) is being driven at the
D C
are accepted or provided When
High
High
High
High
must eventually be asserted to
Low
Low
Low
Low
NA
BS16 )
W R
High
High
High
High
Low
Low
Low
Low
D C
Table 5-2 Bus Cycle Definition
M IO
INTERRUPT ACKNOWLEDGE
does not occur
I O DATA READ
I O DATA WRITE
MEMORY CODE READ
HALT
Address
(BE0
MEMORY DATA READ
MEMORY DATA WRITE
BE1
BE2
BE3
A2 – A31 Low)
hold times t
sections of 5 4 Bus Functional Description
5 2 6 4 NEXT ADDRESS REQUEST (NA )
This is used to request address pipelining This input
indicates the system is prepared to accept new val-
ues of BE0 – BE3
M IO
current cycle is not being acknowledged on
READY
the next address is driven onto the bus provided the
next bus request is already pending internally See
5 4 2 Address Pipelining and 5 4 3 Read and
Write Cycles NA
hold times t
5 2 6 5 BUS SIZE 16 (BS16 )
The BS16
ly connect to 32-bit and 16-bit data buses Asserting
this input constrains the current bus cycle to use
only the lower-order half (D0 – D15) of the data bus
corresponding to BE0
BS16
BE1
during bus cycles asserting BE2
ing BS16
to make adjustments for correct transfer of the up-
per bytes(s) using only physical data signals D0 –
D15
If the operand spans both halves of the data bus
and BS16
matically perform another 16-bit bus cycle BS16
must always meet setup and hold times t
for correct operation
High
High
Low
High
e
Bus Cycle Type
2
are asserted in the current cycle However
from the Intel386 DX even if the end of the
has no additional effect if only BE0
If this input is asserted when sampled
19
will automatically cause the Intel386 DX
15
feature allows the Intel386 DX to direct-
is asserted the Intel386 DX will auto-
and t
and t
SHUTDOWN
Address
(BE0
BE1
BE2
BE3
A2 – A31 Low)
20
16
must always meet setup and
for correct operation See all
A2 – A31 W R
for correct operation
Low
High
High
High
e
and BE1
0
or BE3
Some Cycles
Some Cycles
Locked
D C
17
Yes
Asserting
No
No
No
No
and t
and or
assert-
and
18