A80386DX33 Intel, A80386DX33 Datasheet - Page 137

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

10 REVISION HISTORY
This Intel386 DX data sheet version -005 contains updates and improvements to previous versions A revi-
sion summary is listed here for your convenience
The sections significantly revised since version -001 are
2 9 6
2 9 7
2 11 2
2 12
3 1
4 4 3 3
Figures 4-15a 4-15b
4 6 4
4 6 6
5 6
5 8
5 8 1
Table 6-3
7
Figures 7-8 7-9 7-10
6 2 3 4
The sections significantly revised since version -002 are
Table 2-5
Figure 4-15a
Figure 5-28
5 7
9 4
9 5
Table 6-1
The sections significantly revised since version -003 are
Table 2-6b
2 9 8
Figure 4-5
5 4 3 4
Figures 5-16 5-17
5-19 5-22
9 5
Sequence of exception checking table added
Instruction restart revised
TLB testing revised
Debugging support revised
LOCK prefix restricted to certain instructions
I O privilege level and I O permission bitmap added
I O permission bitmap added
Protection and I O permission bitmap revised
Entering and leaving virtual 8086 mode through task switches trap and interrupt
gates and IRET explained
Self-test signature stored in EAX
Coprocessor interface description added
Software testing for coprocessor presence added
PGA package thermal characteristics added
Designing for ICE-Intel386 revised
ICE-Intel386 clearance requirements added
Encoding of 32-bit address mode with no ‘‘sib’’ byte corrected
Interrupt vector assignments updated
Bit map offset must be less than or equal to DFFFH
Intel386 DX outputs remain in their reset state during self-test
Component and revision identifier history updated
20 MHz D C specifications added
16 MHz A C specifications updated 20 MHz A C specifications added
Clock counts updated
Interrupt priorities 2 and 3 interchanged
Double page faults do not raise double fault exception
Maximum-sized segments must have segments Base
BS16
BS16
sampled asserted in the current bus cycle
16 MHz and 20 MHz A C specifications revised All timing parameters are now
guaranteed at 1 5V test levels The timing parameters have been adjusted to
remain compatible with previous 0 8V 2 0V specifications
timing corrected
timing corrected BS16
must not be asserted once NA
Intel386
TM
DX MICROPROCESSOR
11 0
e
0
has been
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