A80386DX33 Intel, A80386DX33 Datasheet - Page 63

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

transfers automatically generated for Intel386 DX-to-
coprocessor communication use I O addresses
800000F8H through 800000FFH so A31 HIGH in
conjunction with M IO
tion of the coprocessor select signal
The Byte Enable outputs BE0 – BE3
dicate which bytes of the 32-bit data bus are in-
volved with the current transfer This is most conve-
nient for external hardware
The number of Byte Enables asserted indicates the
physical size of the operand being transferred (1 2
3 or 4 bytes) Refer to section 5 3 6 Operand Align-
ment
When a memory write cycle or I O write cycle is in
progress and the operand being transferred occu-
pies only the upper 16 bits of the data bus (D16 –
D31) duplicate data is simultaneously presented on
the corresponding lower 16-bits of the data bus
(D0–D15) This duplication is performed for optimum
write performance on 16-bit buses The pattern of
write data duplication is a function of the Byte En-
ables asserted during the write cycle Table 5-1 lists
the write data present on D0 – D31 as a function of
the asserted Byte Enable outputs BE0 – BE3
BE3
High
High
High
High
High
High
Low
Low
Low
Low
Key
Intel386
BE2
D
C
B
A
High
High
High
High
BE0
BE1
BE2
BE3
Low
Low
Low
Low
Low
Low
TM
e
e
e
e
DX Byte Enables
logical write data d8 – d15
logical write data d0 – d7
logical write data d24 – d31
logical write data d16– d23
applies to D0– D7
applies to D8– D15
applies to D16 – D23
applies to D24 – D31
Table 5-1 Write Data Duplication as a Function of BE0 – BE3
BE1
High
High
High
High
Low
Low
Low
Low
Low
Low
LOW allows simple genera-
BE0
High
High
High
High
High
High
Low
Low
Low
Low
directly in-
D24 – D31
undef
undef
undef
undef
undef
undef
D
D
D
D
Intel386
D16 – D23
5 2 5 Bus Cycle Definition Signals
These three-state outputs define the type of bus cy-
cle being performed W R
write and read cycles D C
data and control cycles M IO
tween memory and I O cycles LOCK
guishes between locked and unlocked bus cycles
The primary bus cycle definition signals are W R
D C
en valid as the ADS
driven asserted The LOCK
same time as the first locked bus cycle begins
which due to address pipelining could be later than
ADS
dress The LOCK
input terminates the last bus cycle which was
locked
Exact bus cycle definitions as a function of W R
D C
combination of W R
given when ADS
nation which is listed as ‘‘does not occur ’’ may oc-
cur during idle bus states when ADS
ed) If M IO
ADS
simplified by using this definition of the ‘‘does not
occur’’ combination
undef
undef
undef
undef
C
C
C
C
C
C
TM
and M IO
is driven asserted See 5 4 3 4 Pipelined Ad-
and M IO
asserted then a decoding scheme may be
DX Write Data
(W R
Intel386
D8 – D15
undef
undef
D C
B
D
B
B
D
B
B
B
D C
is asserted (however that combi-
since these are the signals driv-
TM
are given in Table 5-2 Note one
is negated when the READY
DX MICROPROCESSOR
and W R
D C
(Address Status output) is
D0 – D7
undef
undef
undef
undef
M IO
A
C
A
C
A
A
distinguishes between
distinguishes between
is driven valid at the
and M IO
distinguishes be-
are qualified by
Duplication
Automatic
LOCK )
is not assert-
Yes
Yes
Yes
No
No
No
No
No
No
No
is never
distin-
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