A80386DX33 Intel, A80386DX33 Datasheet - Page 88

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

Intel386
The LOCK
of the first interrupt acknowledge cycle until the end
of the second interrupt acknowledge cycle Four idle
bus states Ti are inserted by the Intel386 DX be-
tween the two interrupt acknowledge cycles allow-
ing for compatibility with spec TRHRL of the 8259A
Interrupt Controller
During both interrupt acknowledge cycles D0– D31
float No data is read at the end of the first interrupt
acknowledge cycle At the end of the second inter-
rupt acknowledge cycle the Intel386 DX will read an
external interrupt vector from D0 – D7 of the data
bus The vector indicates the specific interrupt num-
ber (from 0– 255) requiring service
88
TM
DX MICROPROCESSOR
output is asserted from the beginning
Figure 5-23 Halt Indication Cycle
5 4 5 Halt Indication Cycle
The Intel386 DX halts as a result of executing a
HALT instruction Signaling its entrance into the halt
state a halt indication cycle is performed The halt
indication cycle is identified by the state of the bus
definition signals shown in 5 2 5 Bus Cycle Defini-
tion and a byte address of 2 BE0
the only signals distinguishing halt indication from
shutdown indication which drives an address of 0
During the halt cycle undefined data is driven on
D0 – D31 The halt indication cycle must be acknowl-
edged by READY
A halted Intel386 DX resumes execution when INTR
(if interrupts are enabled) or NMI or RESET is as-
serted
asserted
and BE2
231630 –27
are