A80386DX33 Intel, A80386DX33 Datasheet - Page 26

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

Intel386
A special case of the two byte software interrupt INT
n is the one byte INT 3 or breakpoint interrupt By
inserting this one byte instruction in a program the
user can set breakpoints in his program as a debug-
ging tool
A final type of software interrupt is the single step
interrupt It is discussed in section 2 12
2 9 6 Interrupt and Exception
Interrupts are externally-generated events Maska-
ble Interrupts (on the INTR input) and Non-Maskable
Interrupts (on the NMI input) are recognized at in-
struction boundaries When NMI and maskable
INTR are both recognized at the same instruction
boundary the Intel386 DX invokes the NMI service
routine first If after the NMI service routine has
been invoked maskable interrupts are still enabled
then the Intel386 DX will invoke the appropriate in-
terrupt service routine
Exceptions are internally-generated events Excep-
tions are detected by the Intel386 DX if in the
course of executing an instruction the Intel386 DX
detects a problematic condition The Intel386 DX
then immediately invokes the appropriate exception
service routine The state of the Intel386 DX is such
that the instruction causing the exception can be re-
started If the exception service routine has taken
care of the problematic condition the instruction will
execute without causing the same exception
It is possible for a single instruction to generate sev-
eral exceptions (for example transferring a single
operand could generate two page faults if the oper-
and location spans two ‘‘not present’’ pages) How-
ever only one exception is generated upon each at-
tempt to execute the instruction Each exception
service routine should correct its corresponding ex-
ception and restart the instruction In this manner
exceptions are serviced until the instruction exe-
cutes successfully
As the Intel386 DX executes instructions it follows a
consistent cycle in checking for exceptions as
shown in Table 2-6b
26
Table 2-6a Intel386
Invoking Service Routines in Case of
Priorities
Simultaneous External Interrupts
TM
DX MICROPROCESSOR
2 INTR
1 NMI
This cycle is repeated
TM
DX Priority for
as each instruction is executed and occurs in paral-
lel with instruction decoding and execution
Consider the case of the Intel386 DX having just
completed an instruction It then performs the
following checks before reaching the point where
the next instruction is completed
1 Check for Exception 1 Traps from the instruc-
2 Check for Exception 1 Faults in the next in-
3 Check for external NMI and INTR
4 Check for Segmentation Faults that prevented
5 Check for Page Faults that prevented fetching
6 Check for Faults decoding the next instruction
7 If WAIT opcode check if TS
8 If ESCAPE opcode for numeric coprocessor
9 If WAIT opcode or ESCAPE opcode for nu-
10 Check in the following order for each memo-
Note that the order stated supports the concept
of the paging mechanism being ‘‘underneath’’
the segmentation mechanism Therefore for any
given code or data reference in memory seg-
mentation exceptions are generated before pag-
ing exceptions are generated
Table 2-6b Sequence of Exception Checking
tion just completed (single-step via Trap Flag
or Data Breakpoints set in the Debug Regis-
ters)
struction (Instruction Execution Breakpoint set
in the Debug Registers for the next instruc-
tion)
fetching the entire next instruction (exceptions
11 or 13)
the entire next instruction (exception 14)
(exception 6 if illegal opcode exception 6 if in
Real Mode or in Virtual 8086 Mode and at-
tempting to execute an instruction for Protect-
ed Mode only (see 4 6 4) or exception 13 if
instruction is longer than 15 bytes or privilege
violation in Protected Mode (i e not at IOPL or
at CPL
(exception 7 if both are 1)
check if EM
are 1)
meric coprocessor check ERROR
nal (exception 16 if ERROR
ed)
ry reference required by the instruction
a Check for Segmentation Faults that pre-
b Check for Page Faults that prevent trans-
vent transferring the entire memory quanti-
ty (exceptions 11 12 13)
ferring the entire memory quantity (excep-
tion 14)
e
0)
e
1 or TS
e
1 (exception 7 if either
e
input is assert-
1 and MP
input sig-
e
1