GCIXP1240AC Intel, GCIXP1240AC Datasheet - Page 11

• Manufacturer Part Number: GCIXP1240AC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1240AC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837152

2.0
2.1
2.2
2.3
Datasheet
Functional Units
Conventions
StrongARM* Core
The StrongARM* core is the same industry standard 32-bit RISC processor as used in the Intel
StrongARM
applications such as network computers, PDAs, palmtop computers and portable telephones. The
differentiating feature of the StrongARM* processor is that it provides very high performance in a
low-power, compact design. This makes it feasible to combine it with a collection of other
dedicated execution units on the same silicon die.
The StrongARM* core processor and six RISC Microengines provide the processing power
required to forward greater than 3 million Ethernet packets per second through the IXP1240. A
multi-IXP1200 Network Processor Family system scales linearly so that a system comprised of
eight IXP1200s can process over 24 million packets per second.
The designer can partition his/her application by allocating Microengines, threads, and
StrongARM* tasks. If necessary, multiple IXP1200 Network Processor Family devices can be used
to aggregate CPU MIPs, increase data bandwidth, increase port fanout and density, or some
combination of all three metrics.
The StrongARM* core operates at a frequency determined by programming the Phase-Locked
Loop Configuration register (PLL_CFG) and the maximum rated operating frequency of the
IXP1240 device selected. The IXP1240 is currently available with an F
166, 200, or 232 MHz.
Microengines
Six 32-bit, multithreaded RISC Microengines perform data movement and processing without
assistance from the StrongARM* core. Each Microengine has four independent program counters,
zero overhead context switching and hardware semaphores from other hardware units to ensure
that each Microengine can be fully utilized. A Microengine’s powerful ALU and shifter perform
both ALU and shift operations in a single cycle. The instruction set was specifically designed for
networking and communications applications that require bit, byte, word and longword operations
to forward data quickly and efficiently. Each Microengine contains a large amount of local memory
and registers: 8 Kbytes organized as 2048 by 32 bits of high-speed RAM Control Store for program
execution, 128 32-bit General Purpose Registers, and 128 32-bit transfer registers to service the
SRAM and SDRAM Units.
The Microengines operate at the core clock frequency (F
•
•
In all signal descriptions, an active low signal is indicated by the _L in the signal name.
In this and related IXP1240 documents, a word is equal to 16 bits, a longword is equal to 32
bits, and a quadword is equal to 64 bits. StrongARM* processor documents and the ARM*
V4.0 Architecture Reference typically refer to a word as being equal to 32 bits, and a halfword
as being equal to 16 bits.
*
SA-1100. It is compatible with the StrongARM* processor family currently used in
core
Intel
).
®
IXP1240 Network Processor
core
operating frequency of
®
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