GCIXP1240AC Intel, GCIXP1240AC Datasheet - Page 12

• Manufacturer Part Number: GCIXP1240AC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1240AC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837152

Intel
2.4
2.4.1
12
®
IXP1240 Network Processor
FBI Unit and the IX Bus
The FBI Unit is responsible for servicing fast peripherals, such as MAC-layer devices, on the IX
Bus. This includes moving data to and from the IXP1240 Receive and Transmit FIFOs.
The IX Bus provides a 4.4 Gbps interface to peripheral devices. The IX Bus was specifically
designed to provide a simple and efficient interface. The IX Bus can be configured as either a
64-bit bidirectional bus or as two 32-bit unidirectional buses. The maximum operating frequency
of the IX Bus is 104 MHz.
Two IXP1200 Network Processor Family devices can be placed on a single IX Bus in shared IX
Bus mode. This option is supported only in 64-bit bidirectional mode.
The FBI Unit contains the Transmit and Receive FIFO elements, control and status registers
(CSRs), a 4 Kbyte Scratchpad RAM, and a Hash Unit for generating 48- and 64-bit hash keys. It
also contains the drivers and receivers for the IX Bus.
The IX Bus consists of 64 data pins, 23 control pins, and a clock input pin. A sideband bus
operating in parallel to the IX Bus, called the Ready Bus, consists of eight additional data pins and
five control pins.
The Ready Bus is synchronous to the IX Bus clock, but operation is controlled by a programmable
hardware sequencer. Ready Bus cycles are separate and distinct from IX Bus cycles. Up to twelve
sequencer commands are loaded at chip initialization time, and run in a continuous loop. The
commands can consist of sampling FIFO status for the IX Bus devices, sending Flow Control
messages to MAC devices, and reads/writes to other IXP1200 Network Processor Family devices
as required by the application design. Refer to the IXP1200 Network Processor Family Hardware
Reference Manual for specific details on using the Ready Bus.
IX Bus Access Behavior
There are two basic modes of IX Bus operation. This is a configuration option only and is not
intended to be used “on the fly” to switch between modes.
Each basic mode has two additional modes depending on the number of IX Bus devices and ports
being used: 1-2 MAC mode for one or two slave devices, and 3+ MAC mode when using three to
seven slave devices. Bus timing and the functions of the IX Bus signals are slightly different in
each mode. These functional definitions per IX Bus mode are listed in
•
•
64-Bit Bidirectional Mode
The entire 64-bit data path FDAT[63:0] is used for reads or writes to IX Bus devices. The
IXP1240 always drives and receives all 64 bits of the IX Bus in this mode. Valid bytes are
indicated on the FBE_L[7:0] signals driven by the IXP1240 during writes and by the IX Bus
slave device on reads.
32-Bit Unidirectional Mode
The IX Bus is split into independent 32-bit transmit and 32-bit receive data paths. Transmit
data is driven on FDAT[63:32] and receive data is input on FDAT[31:0]. In this mode, the
transmit path is always driven. The receive path is an input during receive cycles and driven by
the IXP1240 during device reset cycles or during prolonged idle time on the bus. Valid bytes
are identified for the transmit path by the FBE_L[7:4] signals. Valid bytes are identified for the
receive path by the FBE_L[3:0] signals.
Section 3.6
and
Section
Datasheet
3.7.