GCIXP1240AC Intel, GCIXP1240AC Datasheet - Page 6

• Manufacturer Part Number: GCIXP1240AC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1240AC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837152

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IXP1240 Network Processor
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32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 1st
Through 13th Data Return with Status (13th Data Return Shown) ................... 104
32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP, 64-Bit
Status ................................................................................................................ 105
32-Bit Unidirectional IX Bus Timing - Consecutive Receives, Two Element
Transfers with 32-Bit Status .............................................................................. 106
32-Bit Unidirectional IX Bus Timing - Consecutive Transmits, EOP ................. 107
32-Bit Unidirectional IX Bus Timing - Consecutive Transmits with Prepend,
EOP................................................................................................................... 108
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Same
Port, EOP, No Status, FP_READY_WAIT=0 .................................................... 109
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Same
Port, EOP, No Status, FP_READY_WAIT=5 .................................................... 110
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Same
Port, EOP, with Status, FP_READY_WAIT=0 .................................................. 111
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Same
Port, EOP, No Status, FP_READY_WAIT=5 .................................................... 112
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Same
Port, EOP, No Status, FP_READY_WAIT=0, Cancelled Request.................... 113
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Same
Port, No EOP, FP_READY_WAIT=Don’t Care ................................................. 114
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Different
Ports, EOP, No Status, FP_READY_WAIT=0 .................................................. 115
64-Bit Bidirectional IX Bus Timing - Consecutive FastPort Receives, Different
Ports, EOP, No Status, FP_READY_WAIT=0, Cancelled Request .................. 116
Consecutive Fetch Ready Flags, 1-2 MAC Mode (with No External Registered
Decoder) - RDYBUS_TEMPLATE_CTL[10]=1 ................................................. 117
Consecutive Fetch Ready Flags, 3+ MAC Mode (with External Decoder) -
RDYBUS_TEMPLATE_CTL[10]=0 ................................................................... 117
Fetch Ready Flags, Get/Send Commands, 3+ MAC Mode (with External
Registered Decoder) - RDYBUS_TEMPLATE_CTL[10]=0 ............................... 118
Ready Bus Control Timing, Fetch Ready Flags - Flow Control - Fetch Ready
Flags, 1-2 MAC Mode (with No External Registered Decoder) -
RDYBUS_TEMPLATE_CTL[10]=1 ................................................................... 118
Ready Bus Control Timing, Fetch Ready Flags - Flow Control - Fetch Ready
Flags, 3+ MAC Mode (with External Registered Decoder) -
RDYBUS_TEMPLATE_CTL[10]=0 ................................................................... 119
IX Bus Ownership Passing................................................................................ 120
SRAM SCLK Signal AC Parameter Measurements.......................................... 120
SRAM Bus Signal Timing.................................................................................. 122
Pipelined SRAM Read Burst of Eight Longwords ............................................. 124
Pipelined SRAM Write Burst of Eight Longwords ............................................. 125
Pipelined SRAM Read Burst of Four From Bank 0 Followed by Write Burst of
Four From Bank 8 ............................................................................................. 126
Pipelined SRAM Longword Write Followed by 2 Longword Burst Read
Followed by 4 Longword Burst Write ................................................................ 127
Flowthrough SRAM Read Burst of Eight Longwords ........................................ 128
BootROM Read................................................................................................. 129
BootROM Write ................................................................................................. 130
Pipelined SRAM Two Longword Burst Read Followed by BootROM Write ...... 131
SRAM SlowPort Read....................................................................................... 132
SRAM SlowPort Write ....................................................................................... 133
SRAM SlowPort ................................................................................................ 134
Datasheet