GCIXP1240AC Intel, GCIXP1240AC Datasheet - Page 39

• Manufacturer Part Number: GCIXP1240AC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1240AC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837152

Datasheet
Table 18. PCI Interface Pins (Continued)
DEVSEL_L
IDSEL
PERR_L
SERR_L
PCI_IRQ_L
PCI_RST_L
PCI_CLK
PCI_CFN[1:0]
Signal Names
PCI Interface
D13
C16
A11
B11
A22
C21
D20
A24
C23
Pin #
I2/O2/
STS
I2
I2/O2/
STS
I2/O2/
OD
I2/O2/
OD
I2/O2/
TS
I2
I2
Type
1
1
1
1
1
1
1
2
Total
Device Select. Indicates that the target has decoded its address
as the target of the current access. The IXP1240 drives as target
and receives as initiator.
Initialization Device Select. Used as Chip Select during PCI
Configuration Space read and write transactions.
Parity error. Used to report data parity errors. The IXP1240
asserts this when it receives bad data parity as target of a write or
master of a read.
System Error.
As an input, it can cause an interrupt to the StrongARM* core if
the IXP1240 is selected for PCI Central Function and arbitration
support (PCI_CFN[1:0]=11).
As an output it can be asserted by the IXP1240 by writing the
SERR bit in the PCI control register, or in response to a PCI
address parity error when not providing PCI Central Function and
arbitration support (PCI_CFN[1:0]=00).
PCI Interrupt Request.
As output, used to interrupt the PCI Host Processor. It is asserted
when there is a doorbell set or there are messages on the I
outbound post list. This is usually connected to INTA_L on the
PCI Bus.
As Input, It is asserted when there is a doorbell set or there are
messages on the I 2 O outbound post list.
PCI Reset.
PCI Clock input. Reference for PCI signals and internal
operations. PCI clock is typically 33 to 66 MHz.
PCI Central Function and arbitration select inputs. Sampled on
the rising edge of RESET_IN_L.
When = 11, the IXP1240 provides the PCI Central Function and
arbitration support and:
When = 00, PCI Central Function and arbitration is disabled and:
Values of 10 and 01 are reserved for future use.
• When providing PCI Central Function and arbitration support
• When not providing PCI Central Function and arbitration
• PCI_RST_L is an output asserted by the PCI Unit when
• IXP1240 provides bus parking during reset.
• SERR_L is an input that can generate an interrupt to the
• PCI_RST_L is an input asserted by the Host processor.
• The IXP1240 does not provide bus parking during reset.
(PCI_CFN[1:0]=11), PCI _RST_L is an output controlled by
the StrongARM* core. Used to reset the PCI Bus.
(PCI_CFN[1:0]=00), PCI_RST_L is an input, and when
asserted resets the IXP1240 StrongARM* core, all registers,
all transaction queues, and all PCI related state.
initiated by the StrongARM* core.
StrongARM* core.
Intel
Pin Descriptions
®
IXP1240 Network Processor
2
O
39