GCIXP1240AC Intel, GCIXP1240AC Datasheet - Page 14

• Manufacturer Part Number: GCIXP1240AC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1240AC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837152

Intel
2.4.1.1
14
Table 4.
®
IXP1240 Network Processor
32-bit IX Bus Receive Remainder Cycles, with Status Transfer
In both 32-bit and 64-bit modes, all of the associated FBE_L signals (FBE_L[7:4] in 32-bit mode
and FBE_L[7:0] for 64-bit mode) are driven low on a transmit. The last bus transfer, identified by
the assertion of EOP in 64-bit mode or by EOP32 in 32-bit mode, indicates the number of valid
bytes of this last transfer by driving only the valid FBE_L signals.
Similarly for receive cycles, in both 32-bit and 64-bit modes, all associated FBE_L signals must be
driven low by the peripheral or MAC device. The FBE_L signals must identify the number of valid
bytes on the last transfer driven with EOP. The IXP1240 uses this information to update the
RCV_CTL register’s Valid Bytes field. Driving fewer than the four or eight FBE_Ls, except for the
last transfer with EOP, may cause undefined behavior.
Reset and Idle Bus Considerations
While the IXP1240 is in reset, or when the IX Bus is idle for at least 4 FCLK cycles and no bus
requests are pending, the IXP1240 drives the pins listed below. This is done so that the bus is not
left in a high-Z state for a prolonged period of time. This allows the designer to avoid the use of
keeper resistors on the pins to maintain valid levels.
FDAT[63:0]
FBE_L[7:0]
FPS[2:0]
TXASIS
RDYBUS[7:0]
RDYCTL_L[3:0]
RDYCTL_L[4]
EOP
SOP
EOP32
SOP32
RXFAIL
In shared IX Bus mode, pullups should be used on PORTCTL_L[3:0], FPS[2:0], and TXASIS to
maintain valid logic levels during bus exchanges.
In configurations where two IXP1240s are in Shared IX Bus Mode, the IXP1240s must be reset
synchronously, preferably with the same signal driving RESET_IN_L. During reset, the IXP1240s
drive the pins listed above to identical logic states thereby avoiding logic state contention. If the
two devices are not reset synchronously, bus contention could result if one of the devices is held in
reset while the alternate device assumes the role of initial IX Bus owner and begins driving
transactions. This would result in obvious bus malfunction, and over time could affect device
reliability due to resulting high current conditions in the device.
Status
transfer
# of Don’t Care cycles:
NOTE:
1. Status transfer occurs on one or two subsequent IX Bus cycles.
32-bit status
64-bit status
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