GCIXP1240AC Intel, GCIXP1240AC Datasheet - Page 19

• Manufacturer Part Number: GCIXP1240AC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1240AC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837152

Datasheet
Figure 4. SRAM Unit Block Diagram
The SRAM Bus consists of 19 address bits, 32 data bits, 4 chip enable bits, 8 buffer and read/write
control signals, a synchronous output clock (SCLK) running at one-half the IXP1240 core
frequency, and a synchronous input clock (NA/SACLK). When using Flowthru SRAM types, it is
recommended to route the SCLK signal from the SRAMs back to the NA/SACLK input. Routing
this trace identically to the DQ data signals will skew the NA/SACLK slightly to track the return
data trace propagation delay. When using Pipelined/DCD SRAMs, the NA/SACLK input is not
used and may be held inactive with a pulldown to GND to save power.
The SRAM Unit receives memory requests from seven sources: the StrongARM* core and each of
the six Microengines. Refer to the IXP1200 Network Processor Family Hardware Reference
Manual for details on the prioritization and queues provided for servicing these requests.
The IXP1240 supports the use of an optional asynchronous ready input for flexibility in interfacing
memory-mapped I/O devices to the SRAM Slowport region. This will allow the I/O device to add
wait-states to IXP1240 I/O accesses. This function is supported on the HIGH_EN_L pin. An I/O
device must drive HIGH_EN_L with a wired-OR open drain buffer configuration, and only drive
the pin when the I/O device is selected.
To use the RDY_L pin function, it must be enabled by setting SRAM_CSR[19]=1. The RDY_L
Pause State Value field located in register SRAM_SLOW_CONFIG[23:16] must be programmed
with the state value at which you choose to pause the internal wait-state logic. This pause state
relates to the other timing parameters programmed into the SRAM_SLOW_CONFIG and
SRAM_SLOWPORT_CONFIG register fields. See
SCC value is the total number of core clocks for the I/O cycle, and the SRWA, SCEA, SRWD, and
SCED values specify the RD/WR and Chip Enable signal assert and deassert times. When the I/O
cycles begins, the SCC value is loaded into the internal state counter and is decremented on each
* Other names and brands may be claimed as the property of others.
** ARM architecture compatible
Pipelined-
BootROM
Flowthru
32KB to
DCD or
SRAM
256KB
8 MB
8MB
to
Peripheral
CPU port)
(i.e., MAC
Device
RD/WR/EN
Signals
Data[31:0]
SCLK
Addr[18:0]
Buffer
Interface
SRAM
Pin
data
addr
& Address
Command
Generator
Decoder
Microengine Data [63:0]
Machine & Registers
Service Priority
(Arbitration)
Figure 73
AMBA Data
Memory/
FIFO
Intel
Microengine Address
& Command Queues
AMBA Address
(High Priority, Read,
Rd/Wr Queue
which illustrates this example. The
®
Readlock Fail
and Order)
IXP1240 Network Processor
AMBA Bus
Interface
Logic
AMBA[31:0]
(from
StrongARM*
Core)
Microengine
Commands &
Addresses
A8545-01
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