GCIXP1240AC Intel, GCIXP1240AC Datasheet - Page 35

• Manufacturer Part Number: GCIXP1240AC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1240AC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837152

Datasheet
Table 15. IX Bus Interface Pins (Continued)
RDYCTL_L[4]
RDYCTL_L[3:0]
RDYBUS[7:0]
SOP
EOP
IX Bus Signal
Names
[3]
[2]
[1]
[0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
AK6
AL6
AJ7
AH8
AK7
AL9
AK9
AJ9
AL8
AK8
AH9
AJ8
AL7
AH12
AJ11
Pin #
I1/O4/
TS
I1/O4/
TS
I1/O4/
TS
I1/O4/
TS
I1/O4
Type
1
4
8
1
1
Total
In 64-bit Bidirectional IX Bus Mode:
In 32-bit Unidirectional Mode:
Bidirectional Ready Control signals.
In 64-bit Bidirectional IX Bus Mode:
In 32-bit Unidirectional Mode:
8-Bit Bidirectional Ready Bus data.
Start of Packet indication.
End of Packet Indication.
• 1-2 MAC mode: Used as an active low flow control enable for
• 3+ MAC mode: Used in conjunction with RDYCTL_L[3:0].
• In a shared IX Bus system the IXP1240 Ready Bus Master
• 1-2 MAC mode: Used as an active low flow control enable for
• 3+ MAC mode: Used as an active low enable for an external
• 1-2 MAC mode: Bits [3:0] are used to enable the transmit or
• 3+ MAC mode: The transmit and receive FIFO Ready, the
• In a shared IX Bus system the IXP1240 Ready Bus Master
• 1-2 MAC mode: Bits [3:0] are used to enable the transmit or
• 3+ MAC mode: The transmit and receive FIFO ready and flow
• Inputs the Transmit and Receive Ready Flags from IX Bus
• Outputs flow control data to IX Bus devices.
• Data bus for interprocessor communications.
• Receive Start of Packet Input in 32-bit unidirectional IX Bus
• Input/Output in 64-bit bidirectional IX Bus mode. Is Receive
• In a shared IX Bus system, this pin will be tri-stated when
• Receive End of Packet Input in 32-bit unidirectional IX Bus
• Input/Output in 64-bit bidirectional IX Bus mode. EOP is
• In a shared IX Bus system, this pin will be tri-stated when
MAC 1 (GPIO[0] used as a flow control enable for MAC 0).
drives this pin. IXP1240 Ready Bus slave devices snoop this
pin.
MAC 1. GPIO[0] is used as a flow control enable for MAC 0.
decoder for the PORTCTL[1:0] signals.
receive FIFO Ready Flags.
flow control, and inter-processor communication enables are
decoded from RDYCTL_L[4:0].
drives this bus. IXP1240 Ready Bus slave devices snoop
these pins as inputs.
receive FIFO Ready Flags.
control enables are decoded from RDYCTL_L[3:0].
devices.
mode.
Start of Packet input during receive cycles.
passing ownership of the IX Bus.
mode.
Transmit End of Packet output according to values
programmed in the TFIFO control field. Is Receive End of
Packet input during receive cycles.
passing ownership of the IX Bus.
Intel
Pin Descriptions
®
IXP1240 Network Processor
35