NQ80331M667SL7NM Intel, NQ80331M667SL7NM Datasheet - Page 12

• Manufacturer Part Number: NQ80331M667SL7NM
• Description: IC I/O PROCESSOR 733MHZ 829-BGA
• Manufacturer: Intel

Specifications of NQ80331M667SL7NM

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 1.35V
• Mounting Type: Surface Mount
• Package / Case: 829-BGA
• Other names: 862506

Intel® 80331 I/O Processor Datasheet
Features
2.3
2.4
2.5
2.6
12
Address Translation Unit
An Address Translation Unit (ATU) allows PCI transactions direct access to the 80331 local
memory. The ATU supports transactions between PCI address space and 80331 address space.
Address translation for the ATU is controlled through programmable registers accessible from both
the PCI interface and the Intel XScale
80331 Secondary PCI interface of the bridge. Upstream access to the Primary PCI interface is
controlled by inverse decode with the address windows of the bridge. Dual access to registers
allows flexibility in mapping the two address spaces. The ATU also supports the power
management extended capability configuration header that as defined by the PCI Bus Power
Management Interface Specification, Revision 1.1.
Memory Controller
The Memory Controller allows direct control of a DDR SDRAM memory subsystem. It features
programmable chip selects and support for error correction codes (ECC). The memory controller
may be configured for DDR SDRAM at 333 MHz (with 500 MHz and 667 MHz processors) or
DDR-II SDRAM at 400 MHz (with 500 MHz and 800 MHz processors). The memory controller
interface configuration support includes Unbuffered DIMMs, Registered DIMMs, and discrete
DDR SDRAM devices. The memory contoller is dual-ported, with a dedicated interface for the
Intel XScale
External memory may be configured as host addressable memory or private 80331 memory
utilizing the Address Translation Unit and Bridge.
Application Accelerator Unit
The Application Accelerator Unit (AA) provides low-latency, high-throughput data transfer
capability between the AA unit, the 80331 local memory and the PCI bus. It executes data transfers
from and to the 80331 local memory, from the PCI bus to the 80331 local memory, or from the
80331 local memory to the PCI bus. The AA unit performs XOR operations, computes parity,
generates and verifies an eight byte data integrity field, performs memory block fills, and provides
the necessary programming interface. The AAU has been enhanced to support RAID 6 in the D-0
stepping of the 80331.
Peripheral Bus Interface
The Peripheral Bus Interface Unit is a data communication path to the flash memory components
or other peripherals of an 80331 hardware system. The PBI includes support for either 8/16 bit
devices. To perform these tasks at high bandwidth, the bus features a burst transfer capability
which allows successive 8/16-bit data transfers.
®
core Bus Interface Unit and a second interface to the Internal Bus.
November 2004
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core. The PCI interface of the ATU is connected to the
Document Number: 273943-002