NQ80331M667SL7NM Intel, NQ80331M667SL7NM Datasheet - Page 26

• Manufacturer Part Number: NQ80331M667SL7NM
• Description: IC I/O PROCESSOR 733MHZ 829-BGA
• Manufacturer: Intel

Specifications of NQ80331M667SL7NM

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 1.35V
• Mounting Type: Surface Mount
• Package / Case: 829-BGA
• Other names: 862506

Intel® 80331 I/O Processor Datasheet
Package Information
Table 11.
26
Test and Miscellaneous Signals
PWRDELAY
TRST#
Name
Total
TCK
TDO
TMS
PU1
PU2
TDI
N/C
Count
64
72
1
1
1
1
1
1
1
1
Sync(T)
Sync(T)
Sync(T)
Rst(T)
Async
Async
Type
O
-
I
I
I
I
I
I
I
November 2004
Test Clock provides clock input for IEEE 1149.1 Boundary Scan
Testing (JTAG). State information and data are clocked into the
device on the rising clock edge and data is clocked out on the falling
clock edge.
Test Data Input is the JTAG serial input pin. TDI is sampled on the
rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of
the Test Access Port. This signal has a weak internal pull-up to
ensure proper operation when this pin is not being driven.
Test Data Output is the serial output pin for the JTAG feature. TDO
is driven on the falling edge of TCK during the SHIFT-IR and
SHIFT-DR states of the Test Access Port. At other times, TDO
floats. The behavior of TDO is independent of P_RST#.
Test Reset asynchronously resets the Test Access Port controller
function of IEEE 1149 Boundary Scan Testing (JTAG). This pin has
a weak internal pull-up.
Test Mode Select is sampled on the rising edge of TCK to select
the operation of the test logic for IEEE 1149 Boundary Scan testing.
This pin has a weak internal pull-up.
No Connect. Do not connect to any signal, power or ground.
Pullup 1 must be pulled high.
NOTE: This signal was formerly known as P_LOCK#.
Pullup 2 must be pulled high. Is controlled by PCIODT_EN.
NOTE: This signal was formerly known as S_LOCK#.
Power Fail Delay is used to delay the reset of the memory
controller in a power-fail condition. This allows the self-refresh
command to be sent to the DDR SDRAM array.
Description
Document Number: 273943-002