NQ80331M667SL7NM Intel, NQ80331M667SL7NM Datasheet - Page 16

• Manufacturer Part Number: NQ80331M667SL7NM
• Description: IC I/O PROCESSOR 733MHZ 829-BGA
• Manufacturer: Intel

Specifications of NQ80331M667SL7NM

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 1.35V
• Mounting Type: Surface Mount
• Package / Case: 829-BGA
• Other names: 862506

Intel® 80331 I/O Processor Datasheet
Package Information
Table 2.
16
DDR SDRAM Signals
M_CK[2:0]#
M_CK[2:0]
MA[13:0]
CKE[1:0]
DQ[63:0]
DQS[8:0]
CS[1:0]#
M_RST#
DM[8:0]
BA[1:0]
CB[7:0]
Name
RAS#
CAS#
WE#
Total
Count
120
14
64
3
3
1
2
1
1
1
2
2
8
9
9
Sync(M), Rst(M)
Sync(M), Rst(M)
Sync(M), Rst(M)
Sync(M), Rst(M)
Sync(M), Rst(M)
Sync(M), Rst(M)
Sync(M), Rst(M)
Sync(M), Rst(M)
Sync(M), Rst(M)
Sync(M), Rst(M)
Sync(M), Rst(M)
Async
Type
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
November 2004
Memory Clocks are used to provide the positive differential
clocks to the external SDRAM memory subsystem.
Memory Clocks are used to provide the negative differential
clocks to the external SDRAM memory subsystem.
Memory Reset indicates when the memory subsystem has
been reset with P_RST# or a software reset.
Memory Address Bus carries the multiplexed row and
column addresses to the SDRAM memory banks.
SDRAM Bank Address indicates which of the SDRAM
internal banks are read or written during the current
transaction.
SDRAM Row Address Strobe indicates the presence of a
valid row address on the Multiplexed Address Bus MA[12:0].
SDRAM Column Address Strobe indicates the presence of a
valid column address on the Multiplexed Address Bus
MA[12:0].
SDRAM Write Enable indicates that the current memory
transaction is a write operation.
SDRAM Chip Select enables the SDRAM devices for a
memory access (Physical banks 0 and 1).
SDRAM Clock Enable enables the clocks for the SDRAM
memory. Deasserting will place the SDRAM in self-refresh
mode.
SDRAM Data Bus carries 64-bit data to and from memory.
During a data cycle, read or write data is present on one or
more contiguous bytes. During write operations, unused pins
are driven to determinate values.
SDRAM ECC Check Bits carry the 8-bit ECC code to and
from memory during data cycles.
SDRAM Data Strobes carry the strobe signals, output in write
mode and input in read mode for source synchronous data
transfer.
SDRAM Data Mask controls which bytes on the data bus
should be written. When DM[8:0] is asserted, the SDRAM
devices do not accept valid data from the byte lanes.
Description
Document Number: 273943-002