NQ80331M667SL7NM Intel, NQ80331M667SL7NM Datasheet - Page 18

• Manufacturer Part Number: NQ80331M667SL7NM
• Description: IC I/O PROCESSOR 733MHZ 829-BGA
• Manufacturer: Intel

Specifications of NQ80331M667SL7NM

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 1.35V
• Mounting Type: Surface Mount
• Package / Case: 829-BGA
• Other names: 862506

Intel® 80331 I/O Processor Datasheet
Package Information
Table 5.
18
Peripheral Bus Interface Signals
AD[15:0]
A[22:16]
PCE[1]#
PCE[0]#
Name
A[2:0]
POE#
PWE#
Total
ALE
Count
16
31
7
3
1
1
1
1
1
Rst(M)
Rst(M)
Rst(M)
Rst(M)
Rst(M)
Rst(M)
Rst(M)
Rst(M)
Type
I/O
O
O
O
O
O
O
O
November 2004
Address Bus 22:16 carries a demultiplexed version of address bits
A22:16. During address (T
cycles, A22:16 represents the upper seven address bits for the
current access. A22:16 allows the PBI interface to address up to
8 Mbytes per peripheral device.
See
description.
Address/Data Bus carries 16-bit physical addresses and 8-, or
16-bit data to and from memory. During an address (T
2-31 contain a physical word address (bits 0-1 indicate SIZE; see
below). During a data (T
write data, depending on the corresponding bus width.
During write operations to 8-bit wide memory regions, the PBI
drives unused bus pins high or low.
SIZE, which comprises bits 0-1 of the AD lines during a T
specifies the number of data transfers during the bus transaction.
AD1 AD0
See
description.
Address Bus 2:0 carries a demultiplexed version of bits 2:0 of the
AD[15:0] bus. During an address (T
AD[2:0]. During a bursted read data (T
represent the current byte address in the bursted transaction.
A[2:1] are used for an 16-bit wide peripheral while A[1:0] are used
for an 8-bit wide peripheral.
See
description.
Address Latch Enable indicates the transfer of a physical address.
The pin is asserted during the first address cycle and deasserted
during the second address cycle.
Peripheral Output Enable Indicates whether the bus access is a
write or a read with respect to the I/O processor and is valid during
the entire bus access. This pin may be used to control the OE#
input on peripheral devices.
0 = Read
1 = Write
Peripheral Write Enable indicates whether the bus access is a
write or a read with respect to the I/O processor and is valid during
the entire bus access. This pin is use for flash memory accesses
and controls the WE# input on the ROM.
0 = Write
1 = Read
Peripheral Chip Enables specify which of the two memory address
ranges are associated with current bus access. The pin remains valid
during the entire bus access.
Peripheral Chip Enables specify which of the two memory address
ranges are associated with current bus access. The pin remains valid
during the entire bus access.
0
0
1
1
“Table 12, “Reset Strap Signals” on page
“Table 12, “Reset Strap Signals” on page
“Table 12, “Reset Strap Signals” on page
0
1
0
1
1 Transfer
2 Transfers
3 Transfers
4 Transfers
d
) cycle, bits 0-7, or 0-15 contain read or
a
Description
), wait state (T
Document Number: 273943-002
a
) cycle, bits A[2:0] matches
d
) cycle, A[2:0] will
w
) and data cycles (T
27” for a functional
27” for a functional
27” for a functional
a
) cycle, bits
a
cycle,
d
)