NQ80331M667SL7NM Intel, NQ80331M667SL7NM Datasheet - Page 22

• Manufacturer Part Number: NQ80331M667SL7NM
• Description: IC I/O PROCESSOR 733MHZ 829-BGA
• Manufacturer: Intel

Specifications of NQ80331M667SL7NM

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 1.35V
• Mounting Type: Surface Mount
• Package / Case: 829-BGA
• Other names: 862506

Intel® 80331 I/O Processor Datasheet
Package Information
Table 7.
22
Secondary PCI Bus Signals (Sheet 2 of 2)
1. These signal functions are only valid when BRG_EN=0 and ARB_EN=0.
NOTE: When the PCI Bridge is disabled (BRG_EN=0), all secondary PCI interface signals become primary
S_CLKO[3:0]
S_REQ[2,0]#
S_GNT[3,2]#
S_PCIXCAP
S_REQ[3]#/
S_CLKOUT
S_GNT[1]#/
S_GNT[0]#/
S_REQ[1]#
S_RCOMP
S_PERR#
S_CLKIN/
S_M66EN
P_IDSEL
P_GNT#
P_REQ#
P_CLK
P_BMI
Name
Total
interface signals.
1
1
1
1
1
Count
101
1
4
1
1
1
1
1
2
2
1
1
1
1
Sync(S)
Sync(S)
Sync(S)
Sync(S)
Sync(A)
Sync(S)
Sync(S)
Rst(S)
Rst(A)
Rst(S)
Rst(S)
O/OD
Type
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
November 2004
Secondary PCI Bus Parity Error is asserted when a data parity
error during a secondary PCI bus transaction.
Secondary PCI Bus Output Clocks are used to drive external
logic on the secondary PCI bus.
Secondary PCI Bus Output Clock is used to drive S_CLKIN
when the IO processor provides secondary bus clocks.
Secondary PCI Bus Input Clock provides the timing for all PCI
transactions. Typically connected on the board to S_CLKOUT.
Provides the timing clock for all secondary PCI interfaces.
When the PCI Bridge is disabled (BRG_EN=0), this is the Primary
PCI Input Clock, driven by an external device.
Secondary PCI Bus 66 MHz Enable indicates the speed of the
secondary PCI bus. When this signal is high, the bus speed is 66
MHz and when it is low, the bus speed is 33 MHz.
Secondary PCI Bus Request is the request signal from device 3
on the secondary PCI bus.
When the PCI Bridge is disabled (BRG_EN=0), this pin functions
as PCI Bus Initialization Device Select and is used to select the
80331 during a Configuration Read or Write command on the PCI
bus.
Secondary PCI Bus Request is the request signal from device 1
on the secondary PCI bus.
When the PCI Bridge is disabled (BRG_EN=0), this pin functions
as Primary PCI Bus Grant indicating that access to the PCI bus
has been granted.
Secondary PCI Bus Requests are the request signals from
devices 2 and 0 on the secondary PCI bus.
Secondary PCI Bus Grants are grant signals sent to devices
3 and 2 on the secondary PCI bus.
Secondary PCI Bus Grant is a grant signal sent to device 1 on
the secondary PCI bus.
When the PCI Bridge is disabled (BRG_EN=0), this pin functions
as Primary PCI Bus Request and indicates to the PCI bus arbiter
that the I/O processor desires use of the PCI bus.
Secondary PCI Bus Grant is a grant signal sent to device 0 on
the secondary PCI bus.
When the PCI Bridge is disabled (BRG_EN=0), this pin functions
as PCI Bus Master Indicator to be used with external RAIDIOS
logic for private device control.
Secondary PCI-X Capability is an analog pad that selects PCI/X
mode and frequency capabilities. Non-standard, special purpose
analog pin.
PCI Resistor Compensation Pin is an analog pad that connects to
the board resistor to control all PCI output driver strengths (analog).
Description
Document Number: 273943-002