NQ80331M667SL7NM Intel, NQ80331M667SL7NM Datasheet - Page 23

• Manufacturer Part Number: NQ80331M667SL7NM
• Description: IC I/O PROCESSOR 733MHZ 829-BGA
• Manufacturer: Intel

Specifications of NQ80331M667SL7NM

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 1.35V
• Mounting Type: Surface Mount
• Package / Case: 829-BGA
• Other names: 862506

Document Number: 273943-002
Table 8.
Table 9.
Interrupt Signals
I
2
C Signals
P_INT[D:A]#
S_INT[D:A]#
Name
Name
SCD0
SCD1
SCL0
SCL1
HPI#
Total
Total
Count
Count
4
4
1
9
1
1
1
4
1
Rst(P)
Rst(S)
Async
Async
Async
Type
Type
OD
I/O
I/O
I/O
I/O
November 2004
O
I
I
Primary PCI Bus Interrupt requests an interrupt. The assertion and
deassertion of P_INT[D:A]# is asynchronous to P_CLK. A device
asserts its P_INT[D:A]# line when requesting attention from its
device driver. Once the P_INT[D:A]# signal is asserted, it remains
asserted until the device driver clears the pending request.
P_INT[D:A]# interrupts are level sensitive.
Secondary PCI Bus Interrupt requests an interrupt. The assertion
and deassertion of S_INT[D:A]# is asynchronous to S_CLKIN. A
device asserts its S_INT[D:A]# line when requesting attention from
its device driver. Once the S_INT[D:A]# signal is asserted, it
remains asserted until the device driver clears the pending request.
S_INT[D:A]# interrupts are level sensitive.
High Priority Interrupt causes a high priority interrupt to the I/O
processor. This pin is level-detect only and is internally
synchronized.
I
I
I
2
2
2
I
2
C Clock provides synchronous operation of the I
C Data is used for data transfer and arbitration of the I
C Clock provides synchronous operation of the I
C Data is used for data transfer and arbitration of the I
Intel® 80331 I/O Processor Datasheet
Description
Description
Package Information
2
2
C bus zero.
C bus one.
2
2
C bus zero.
C bus one.
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