NQ80331M667SL7NM Intel, NQ80331M667SL7NM Datasheet - Page 27

• Manufacturer Part Number: NQ80331M667SL7NM
• Description: IC I/O PROCESSOR 733MHZ 829-BGA
• Manufacturer: Intel

Specifications of NQ80331M667SL7NM

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 1.35V
• Mounting Type: Surface Mount
• Package / Case: 829-BGA
• Other names: 862506

Document Number: 273943-002
Table 12.
Reset Strap Signals (Sheet 1 of 2)
S_PCIX133EN
CORE_RST#
P_BOOT16#
MEM_TYPE
PRIVMEM
PRIVDEV
RETRY
Name
Count
1
1
1
1
1
1
1
Config
Config
Config
Type
November 2004
C
C
C
C
Configuration Retry Mode: RETRY is latched on the rising
(deasserting) edge of P_RST# and determines when the PCI interface
of the ATU will disable PCI configuration cycles by signaling a retry
until the configuration cycle retry bit is cleared in the PCI configuration
and status register.
0 = Configuration Cycles enabled (Requires pull down resistor.)
1 = Configuration Retry enabled in the ATU (Default mode)
NOTE: Muxed onto signal AD[6], see
Core Reset Mode is latched on the rising (deasserting) edge of
P_RST# and determines when the Intel XScale
until the processor reset bit is cleared in PCI configuration and status
register.
0 = Hold in reset. (Requires pull-down resistor.)
1 = Do not hold in reset. (Default mode)
NOTE: Muxed onto signal AD[5], see
Bus Width is latched on the rising (deasserting) edge of P_RST#, it
sets the default bus width for the PBI Memory Boot window.
0 = 16 bits wide (Requires a pull-down resistor.)
1 = 8 bits wide (Default mode)
NOTE: Muxed onto signal AD[4], see
Memory Type: MEM_TYPE is latched on the rising (deasserting)
edge of P_RST# and it defines the speed of the DDR SDRAM
interface.
0 = DDR-II SDRAM at 400 MHz (Required pull-down resistor.)
1 = DDR SDRAM at 333 MHz (Default mode)
NOTE: Muxed onto signal AD[2], see
Secondary PCI Bus 133 MHz Enable: S_PCIX133EN latched on
rising (deasserting) edge of P_RST# and determines maximum
PCI-X mode operating frequency.
0 = 100 MHz enabled (Requires pull down resistor.)
1 = 133 MHz enabled (Default mode)
NOTE: Muxed onto signal AD[3], see
Private Memory Enable: PRIVMEM latched at rising (deasserting)
edge of P_RST# and determines if 80331 operates with Private
Memory Space on the secondary PCI bus of the PCI-to-PCI Bridge.
0 = Normal addressing mode (Requires pull-down resistor)
1 = Private Addressing enable in PCI-to-PCI Bridge. (Default
NOTE: Muxed onto signal A[1], see
Private Device Enable: PRIVDEV latched at rising (deasserting)
edge of P_RST# and determines if 80331 operates with Private
Device enabled on the secondary PCI bus of the PCI-to-PCI
Bridge.
0 = All Secondary PCI devices are accessible to Primary PCI
1 = Private Devices enabled in PCI-to-PCI Bridge. (Default mode)
NOTE: Muxed onto signal A[0], see
mode).
config cycles. (Requires pull-down resistor)
for Functional Modes” on page
for Functional Modes” on page
for Functional Modes” on page
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for Functional Modes” on page
Functional Modes” on page
Functional Modes” on page
Intel® 80331 I/O Processor Datasheet
Description
33.
33.
Table 15, “Pin Multiplexing for
Table 15, “Pin Multiplexing for
Table 15, “Pin Multiplexing
Table 15, “Pin Multiplexing
Table 15, “Pin Multiplexing
Table 15, “Pin Multiplexing
Table 15, “Pin Multiplexing
Package Information
33.
33.
33.
33.
33.
®
core is held in reset
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